Build starting @ 2019-03-05T07:08:23.627318 Running make -C /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid run (with MAKEFLAGS=' -j --jobserver-fds=3,4') --------------------------------------------------------------------------- make[1]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make clean make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' rm -rf build run.ok cd clb && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' cd clb_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' cd iob && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' cd iob_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' cd mmcm && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' cd pll && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' cd ps7_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' cd bram && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' cd bram_block && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' cd bram_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' cd dsp && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' cd dsp_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' cd fifo_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' cd monitor && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' cd monitor_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' cd cfg_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' cd orphan_int_column && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' cd clk_hrow && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' cd clk_bufg && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make database make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' bash generate.sh build/tiles tiles ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate_tiles.tcl # source "$::env(FUZDIR)/util.tcl" ## proc min_ysite { duts_in_column } { ## # Given a list of sites, return the one with the lowest Y coordinate ## ## set min_dut_y 9999999 ## ## foreach dut $duts_in_column { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## if { $dut_y < $min_dut_y } { ## set selected_dut $dut ## set min_dut_y $dut_y ## } ## } ## return $selected_dut ## } ## proc group_dut_cols { duts ypitch } { ## # Group a list of sites into pitch sized buckets ## # Ex: IOBs occur 75 to a CMT column ## # Set pitch to 75 to get 0-74 in one bucket, 75-149 in a second, etc ## # X0Y0 {IOB_X0Y49 IOB_X0Y48 IOB_X0Y47 ... } ## # Anything with a different x is automatically in a different bucket ## ## # LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column) ## set dut_columns "" ## foreach dut $duts { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## # 75 per column => 0, 75, 150, etc ## set y_column [expr ($dut_y / $ypitch) * $ypitch] ## dict append dut_columns "X${dut_x}Y${y_column}" "$dut " ## } ## return $dut_columns ## } ## proc loc_dut_col_bels { dut_columns cellpre cellpost } { ## # set cellpre di ## ## # Pick the smallest Y in each column and LOC a cell to it ## # cells must be named like $cellpre[$dut_index] ## # Return the selected sites ## ## set ret_bels {} ## set dut_index 0 ## ## dict for {column duts_in_column} $dut_columns { ## set sel_bel_str [min_ysite $duts_in_column] ## set sel_bel [get_bels $sel_bel_str] ## if {"$sel_bel" == ""} {error "Bad bel $sel_bel from bel str $sel_bel_str"} ## set sel_site [get_sites -of_objects $sel_bel] ## if {"$sel_site" == ""} {error "Bad site $sel_site from bel $sel_bel"} ## ## set cell [get_cells $cellpre$dut_index$cellpost] ## puts "LOCing cell $cell to site $sel_site (from bel $sel_bel)" ## set_property LOC $sel_site $cell ## ## set dut_index [expr $dut_index + 1] ## lappend ret_bels $sel_bel ## } ## ## return $ret_bels ## } ## proc loc_dut_col_sites { dut_columns cellpre cellpost } { ## set bels [loc_dut_col_bels $dut_columns $cellpre $cellpost] ## set sites [get_sites -of_objects $bels] ## return $sites ## } ## proc make_io_pad_sites {} { ## # get all possible IOB pins ## foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { ## set site [get_sites -of_objects $pad] ## if {[llength $site] == 0} { ## continue ## } ## if [string match IOB33* [get_property SITE_TYPE $site]] { ## dict append io_pad_sites $site $pad ## } ## } ## return $io_pad_sites ## } ## proc make_iob_pads {} { ## set io_pad_sites [make_io_pad_sites] ## ## set iopad "" ## dict for {key value} $io_pad_sites { ## # Some sites have more than one pad? ## lappend iopad [lindex $value 0] ## } ## return $iopad ## } ## proc make_iob_sites {} { ## set io_pad_sites [make_io_pad_sites] ## ## set sites "" ## dict for {key value} $io_pad_sites { ## lappend sites $key ## } ## return $sites ## } ## proc assign_iobs_old {} { ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] ## } ## proc assign_iobs {} { ## # Set all I/Os on the bus to valid values somewhere on the chip ## # The iob fuzzer sets these to more specific values ## ## # All possible IOs ## set iopad [make_iob_pads] ## # Basic pins ## # XXX: not all pads are valid, but seems to be working for now ## # Maybe better to set to XRAY_PIN_* and take out of the list? ## set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb] ## ## # din bus ## set fixed_pins 3 ## set iports [get_ports di*] ## for {set i 0} {$i < [llength $iports]} {incr i} { ## set pad [lindex $iopad [expr $i+$fixed_pins]] ## set port [lindex $iports $i] ## set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port ## } ## } ## proc make_project {} { ## # Generate .bit only over ROI ## make_project_roi XRAY_ROI_TILEGRID ## } ## proc make_project_roi { roi_var } { ## # 6 CMTs in our reference part ## # What is the largest? ## set n_di 16 ## ## create_project -force -part $::env(XRAY_PART) design design ## ## read_verilog "$::env(FUZDIR)/top.v" ## synth_design -top top -verilog_define N_DI=$n_di ## ## assign_iobs ## ## create_pblock roi ## add_cells_to_pblock [get_pblocks roi] [get_cells roi] ## foreach roi "$::env($roi_var)" { ## puts "ROI: $roi" ## resize_pblock [get_pblocks roi] -add "$roi" ## } ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## set_param tcl.collectionResultDisplayLimit 0 ## ## set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## } # proc write_tiles_txt {} { # # Get all tiles, ie not just the selected LUTs # set tiles [get_tiles] # # # Write tiles.txt with site metadata # set fp [open "tiles.txt" w] # foreach tile $tiles { # set type [get_property TYPE $tile] # set grid_x [get_property GRID_POINT_X $tile] # set grid_y [get_property GRID_POINT_Y $tile] # set sites [get_sites -quiet -of_objects $tile] # set typed_sites {} # # if [llength $sites] { # set site_types [get_property SITE_TYPE $sites] # foreach t $site_types s $sites { # lappend typed_sites $t $s # } # } # # puts $fp "$type $tile $grid_x $grid_y $typed_sites" # } # close $fp # } # proc run {} { # # Generate grid of entire part # make_project_roi XRAY_ROI_TILEGRID # # place_design # route_design # write_checkpoint -force design.dcp # write_bitstream -force design.bit # # write_tiles_txt # } # run Command: synth_design -top top -verilog_define N_DI=16 Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2244 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 17322 ; free virtual = 51911 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] Parameter DIN_N bound to: 16 - type: integer Parameter DOUT_N bound to: 108 - type: integer INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-638] synthesizing module 'roi' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized0' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized1' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized2' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized3' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized4' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized5' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized7' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized7' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized8' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized9' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized9' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized10' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized10' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized11' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized11' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized12' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized12' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized13' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized13' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized14' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized14' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized15' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized15' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized16' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized16' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized17' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized17' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized18' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized18' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized19' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized19' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized20' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized20' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized21' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized21' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized22' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized22' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized23' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized23' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized24' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized24' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized25' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized25' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized26' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized26' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized27' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized27' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized28' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized28' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized29' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized29' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized30' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized30' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized31' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized31' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized32' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized32' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized33' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized33' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized34' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized34' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized35' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized35' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized36' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized36' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized37' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized37' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized38' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized38' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized39' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized39' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized40' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized40' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized41' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized41' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized42' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized42' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized43' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized43' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized44' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized44' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized45' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized45' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized46' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized46' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized47' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized47' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized48' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized48' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized49' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized49' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized50' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized50' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized51' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized51' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized52' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized52' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized53' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized53' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized54' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized54' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized55' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized55' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized56' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized56' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized57' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized57' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized58' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized58' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized59' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized59' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized60' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized60' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized61' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized61' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized62' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized62' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized63' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized63' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized64' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized64' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized65' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized65' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized66' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized66' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized67' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized67' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized68' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized68' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized69' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized69' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized70' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized70' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized71' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized71' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized72' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized72' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized73' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized73' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized74' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized74' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized75' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized75' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized76' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized76' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized77' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized77' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized78' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized78' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized79' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized79' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized80' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized80' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized81' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized81' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized82' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized82' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized83' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized83' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized84' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized84' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized85' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized85' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized86' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized86' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized87' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized87' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized88' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized88' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized89' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized89' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized90' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized90' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized91' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized91' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized92' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized92' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized93' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized93' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized94' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized94' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized95' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized95' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized96' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized96' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized97' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized97' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized98' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized98' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'RAMB36E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized0' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized3' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized4' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized5' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized6' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-256] done synthesizing module 'roi' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-256] done synthesizing module 'top' (5#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] WARNING: [Synth 8-3331] design roi has unconnected port clk --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 17307 ; free virtual = 51897 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 17308 ; free virtual = 51898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 17308 ; free virtual = 51898 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'din_reg' and it is trimmed from '16' to '8' bits. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:36] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.953 ; gain = 110.508 ; free physical = 17300 ; free virtual = 51891 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (di_bufs[8].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[9].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[10].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[11].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[12].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[13].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[14].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[14]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[13]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[12]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[11]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[10]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[9]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[8]) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.922 ; gain = 233.477 ; free physical = 17360 ; free virtual = 51950 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.922 ; gain = 233.477 ; free physical = 17359 ; free virtual = 51949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17358 ; free virtual = 51948 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 3| |2 |LUT3 | 108| |3 |LUT6 | 100| |4 |RAMB36E1 | 8| |5 |FDRE | 125| |6 |IBUF | 11| |7 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 356| |2 | roi |roi | 216| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17357 ; free virtual = 51947 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 96 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 17358 ; free virtual = 51949 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.945 ; gain = 243.492 ; free physical = 17358 ; free virtual = 51949 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 230 Infos, 96 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1472.965 ; gain = 390.074 ; free physical = 17302 ; free virtual = 51892 ROI: SLICE_X0Y0:SLICE_X43Y99 ROI: RAMB18_X0Y0:RAMB18_X2Y39 ROI: RAMB36_X0Y0:RAMB36_X2Y19 ROI: DSP48_X0Y0:DSP48_X1Y39 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1536.996 ; gain = 0.000 ; free physical = 17305 ; free virtual = 51895 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17075422c Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1536.996 ; gain = 0.000 ; free physical = 17305 ; free virtual = 51895 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1922.484 ; gain = 0.000 ; free physical = 16892 ; free virtual = 51482 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196761f3e Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16887 ; free virtual = 51478 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16887 ; free virtual = 51478 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16887 ; free virtual = 51478 Phase 1 Placer Initialization | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 16887 ; free virtual = 51478 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16909 ; free virtual = 51499 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16909 ; free virtual = 51499 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18f2ccf33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16909 ; free virtual = 51499 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16909 ; free virtual = 51499 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16909 ; free virtual = 51499 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16906 ; free virtual = 51496 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16906 ; free virtual = 51496 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16906 ; free virtual = 51496 Phase 3 Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16906 ; free virtual = 51496 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16906 ; free virtual = 51496 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16907 ; free virtual = 51498 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16907 ; free virtual = 51498 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1ce33f28d Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16907 ; free virtual = 51498 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ce33f28d Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16907 ; free virtual = 51498 Ending Placer Task | Checksum: 14c774d33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 16918 ; free virtual = 51509 240 Infos, 98 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 2042.543 ; gain = 569.578 ; free physical = 16918 ; free virtual = 51509 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9c4f4a11 ConstDB: 0 ShapeSum: b0280322 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2074.188 ; gain = 31.645 ; free physical = 16696 ; free virtual = 51287 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2079.176 ; gain = 36.633 ; free physical = 16665 ; free virtual = 51256 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2079.176 ; gain = 36.633 ; free physical = 16665 ; free virtual = 51256 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b8accb7e Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16655 ; free virtual = 51245 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: fc55de3b Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16666 ; free virtual = 51256 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16668 ; free virtual = 51258 Phase 4 Rip-up And Reroute | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16668 ; free virtual = 51258 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16668 ; free virtual = 51258 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16680 ; free virtual = 51271 Phase 6 Post Hold Fix | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16682 ; free virtual = 51272 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0324117 % Global Horizontal Routing Utilization = 0.0410751 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. Phase 7 Route finalize | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2093.230 ; gain = 50.688 ; free physical = 16710 ; free virtual = 51300 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2095.230 ; gain = 52.688 ; free physical = 16708 ; free virtual = 51299 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2095.230 ; gain = 52.688 ; free physical = 16708 ; free virtual = 51299 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2095.230 ; gain = 52.688 ; free physical = 16743 ; free virtual = 51333 Routing Is Done. 247 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2134.020 ; gain = 91.477 ; free physical = 16743 ; free virtual = 51333 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2134.020 ; gain = 0.000 ; free physical = 16741 ; free virtual = 51334 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:09:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 257 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2474.125 ; gain = 340.105 ; free physical = 16696 ; free virtual = 51291 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:09:42 2019... mkdir -p build/basicdb cd build && python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate.py \ --tiles /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/tiles.txt \ --out /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/basicdb/tilegrid.json cd iob && make cd iob_int && make cd monitor && make cd bram && make cd bram_block && make cd bram_int && make cd clb && make cd clb_int && make cd dsp && make cd fifo_int && make cd cfg_int && make cd monitor_int && make make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' GENERATE_ARGS="--oneval 1 --design params.csv --dframe 26 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 0 --design params.csv --dframe 14 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 3] # set pin_str [lindex $line 4] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # gets $fp line # # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 2] # set pin_str [lindex $line 3] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4593 Command: synth_design -top top INFO: Helper process launched with PID 4594 Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4604 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4630 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4649 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 4664 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4739 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4778 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4843 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4876 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4952 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4988 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 15007 ; free virtual = 49616 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 14991 ; free virtual = 49600 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 14947 ; free virtual = 49556 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 14930 ; free virtual = 49539 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 14912 ; free virtual = 49521 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 14905 ; free virtual = 49514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.988 ; free physical = 14873 ; free virtual = 49482 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 14850 ; free virtual = 49459 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 14780 ; free virtual = 49389 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 14718 ; free virtual = 49326 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] Starting Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 14708 ; free virtual = 49317 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] WARNING: [Synth 8-350] instance 'dummy_lut' of module 'LUT6' requires 7 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 14727 ; free virtual = 49340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 14730 ; free virtual = 49340 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 14743 ; free virtual = 49353 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 14742 ; free virtual = 49352 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 14742 ; free virtual = 49352 --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 14736 ; free virtual = 49347 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] Report RTL Partitions: WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] No constraint files found. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 14721 ; free virtual = 49331 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 14722 ; free virtual = 49332 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 14723 ; free virtual = 49333 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 14725 ; free virtual = 49335 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1205.945 ; gain = 110.508 ; free physical = 14732 ; free virtual = 49342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 14735 ; free virtual = 49345 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 14772 ; free virtual = 49383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 14774 ; free virtual = 49385 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Parameter SIM_DEVICE bound to: 7SERIES - type: string --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 14744 ; free virtual = 49354 WARNING: [Synth 8-350] instance 'idelayctrl' of module 'IDELAYCTRL' requires 3 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] --------------------------------------------------------------------------------- Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 14740 ; free virtual = 49351 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y11' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y12' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y15' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y16' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y17' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y18' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y21' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y22' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y23' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y24' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y25' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y26' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y27' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y28' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y29' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y30' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y3' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y4' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y33' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y34' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y35' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y36' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y39' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y40' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y41' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y42' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y45' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y46' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y47' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y48' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y5' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 14727 ; free virtual = 49337 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y6' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y9' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y10' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y100' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y149' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y50' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 14726 ; free virtual = 49337 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y99' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y107' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y108' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y119' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y120' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y131' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y132' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y143' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y144' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 14727 ; free virtual = 49337 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y57' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y58' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y69' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y70' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] No constraint files found. WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y81' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y82' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y93' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y94' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y113' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y114' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 14722 ; free virtual = 49332 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y137' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y138' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y63' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y64' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y87' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y88' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y101' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] Detailed RTL Component Info : WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y102' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y103' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y104' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y105' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 14634 ; free virtual = 49244 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.496 ; free physical = 14650 ; free virtual = 49261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14648 ; free virtual = 49258 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14612 ; free virtual = 49223 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14609 ; free virtual = 49220 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1511] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1651] Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.496 ; free physical = 14610 ; free virtual = 49221 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1707] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1903] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2155] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2295] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.523 ; free physical = 14610 ; free virtual = 49221 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2351] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14617 ; free virtual = 49228 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:16] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 14603 ; free virtual = 49214 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2138] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2304] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.523 ; free physical = 14582 ; free virtual = 49193 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2361] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3964] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3982] +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4314] No constraint files found. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4480] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4563] --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4646] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8215] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 14572 ; free virtual = 49183 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 14573 ; free virtual = 49185 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14532 ; free virtual = 49144 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 14530 ; free virtual = 49142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14473 ; free virtual = 49085 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 14473 ; free virtual = 49084 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.953 ; gain = 115.504 ; free physical = 14423 ; free virtual = 49034 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 14349 ; free virtual = 48960 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 14272 ; free virtual = 48884 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 14270 ; free virtual = 48881 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 14171 ; free virtual = 48782 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 14101 ; free virtual = 48713 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 14044 ; free virtual = 48656 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 14042 ; free virtual = 48654 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 13432 ; free virtual = 48044 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 13419 ; free virtual = 48032 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.914 ; gain = 232.477 ; free physical = 13401 ; free virtual = 48013 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 13378 ; free virtual = 48001 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.914 ; gain = 232.477 ; free physical = 13384 ; free virtual = 47997 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13372 ; free virtual = 47985 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13374 ; free virtual = 47987 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 13369 ; free virtual = 47982 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 13351 ; free virtual = 47963 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- No constraint files found. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.234 ; free physical = 13346 ; free virtual = 47959 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 13346 ; free virtual = 47959 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 13346 ; free virtual = 47958 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13336 ; free virtual = 47949 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13339 ; free virtual = 47952 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup Report RTL Partitions: --------------------------------------------------------------------------------- +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.234 ; free physical = 13339 ; free virtual = 47952 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 13336 ; free virtual = 47948 No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 13334 ; free virtual = 47947 Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13334 ; free virtual = 47947 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 13329 ; free virtual = 47942 --------------------------------------------------------------------------------- No constraint files found. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 13328 ; free virtual = 47940 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13318 ; free virtual = 47930 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13317 ; free virtual = 47930 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: Start Flattening Before IO Insertion +-+--------------+------------+----------+ --------------------------------------------------------------------------------- | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 13304 ; free virtual = 47916 --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I1 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I2 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I3 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I4 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I5 to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13302 ; free virtual = 47915 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13301 ; free virtual = 47914 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13300 ; free virtual = 47912 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13299 ; free virtual = 47911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13298 ; free virtual = 47911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13298 ; free virtual = 47911 --------------------------------------------------------------------------------- Report RTL Partitions: --------------------------------------------------------------------------------- +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | Start Writing Synthesis Report +-+--------------+------------+----------+ --------------------------------------------------------------------------------- +-+--------------+------------+----------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT6 | 1| --------------------------------------------------------------------------------- |2 |IBUF | 96| +------+-----+------+ Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 13297 ; free virtual = 47910 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 97| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13297 ; free virtual = 47910 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13297 ; free virtual = 47910 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13296 ; free virtual = 47908 Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13296 ; free virtual = 47908 --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 13297 ; free virtual = 47910 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13296 ; free virtual = 47908 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13296 ; free virtual = 47908 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13296 ; free virtual = 47908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13295 ; free virtual = 47908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13295 ; free virtual = 47908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13293 ; free virtual = 47905 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. INFO: [Project 1-571] Translating synthesized netlist Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.930 ; gain = 242.492 ; free physical = 13279 ; free virtual = 47891 No constraint files found. Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 13280 ; free virtual = 47892 --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 13256 ; free virtual = 47869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13256 ; free virtual = 47868 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13256 ; free virtual = 47868 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13255 ; free virtual = 47868 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13255 ; free virtual = 47868 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13255 ; free virtual = 47868 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13257 ; free virtual = 47869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13257 ; free virtual = 47870 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 13255 ; free virtual = 47868 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13257 ; free virtual = 47869 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13257 ; free virtual = 47870 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13257 ; free virtual = 47870 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13245 ; free virtual = 47857 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13244 ; free virtual = 47856 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13244 ; free virtual = 47856 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13242 ; free virtual = 47855 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13242 ; free virtual = 47855 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13242 ; free virtual = 47855 --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13242 ; free virtual = 47855 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13244 ; free virtual = 47856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 13244 ; free virtual = 47856 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 13244 ; free virtual = 47856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13243 ; free virtual = 47856 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13243 ; free virtual = 47855 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13239 ; free virtual = 47851 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13234 ; free virtual = 47847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 200| |3 |IBUF | 200| +------+-----------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 401| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13225 ; free virtual = 47838 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 402 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13240 ; free virtual = 47852 INFO: [Project 1-571] Translating synthesized netlist Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 13238 ; free virtual = 47850 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13220 ; free virtual = 47833 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13228 ; free virtual = 47840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13228 ; free virtual = 47840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13215 ; free virtual = 47827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13215 ; free virtual = 47827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13214 ; free virtual = 47827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13215 ; free virtual = 47828 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13215 ; free virtual = 47828 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13215 ; free virtual = 47828 --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 13216 ; free virtual = 47828 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13215 ; free virtual = 47827 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 13216 ; free virtual = 47828 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13216 ; free virtual = 47829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13216 ; free virtual = 47829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13216 ; free virtual = 47829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13215 ; free virtual = 47829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13215 ; free virtual = 47829 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13201 ; free virtual = 47817 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 13203 ; free virtual = 47819 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.574 ; gain = 216.121 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47783 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13171 ; free virtual = 47784 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 400 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.574 ; gain = 216.121 ; free physical = 13132 ; free virtual = 47745 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13124 ; free virtual = 47736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13120 ; free virtual = 47733 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13119 ; free virtual = 47731 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13117 ; free virtual = 47729 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13117 ; free virtual = 47729 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13115 ; free virtual = 47727 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13114 ; free virtual = 47726 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13113 ; free virtual = 47725 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13111 ; free virtual = 47723 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 13111 ; free virtual = 47723 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13008 ; free virtual = 47621 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13008 ; free virtual = 47620 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13007 ; free virtual = 47619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13006 ; free virtual = 47619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13007 ; free virtual = 47619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13006 ; free virtual = 47619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13006 ; free virtual = 47618 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 13004 ; free virtual = 47616 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.566 ; gain = 225.105 ; free physical = 13006 ; free virtual = 47618 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 12956 ; free virtual = 47568 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 12897 ; free virtual = 47509 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12648 ; free virtual = 47261 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 12482 ; free virtual = 47094 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1395.723 ; gain = 312.828 ; free physical = 12456 ; free virtual = 47069 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Looping LIOB33_X0Y1 0 IOB_X0Y1 {di[0]} key "IOB_X0Y1" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl" line 77) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:10:26 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.930 ; gain = 338.047 ; free physical = 12507 ; free virtual = 47119 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 12584 ; free virtual = 47197 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' Makefile:57: recipe for target 'iob/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 12882 ; free virtual = 47494 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 12881 ; free virtual = 47493 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y0' at site IDELAY_X0Y0, Site IOB_X0Y0 is not bonded. Place terminal di[0] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y1' at site IDELAY_X0Y1, Site IOB_X0Y1 is not bonded. Place terminal di[14] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y2' at site IDELAY_X0Y2, Site IOB_X0Y2 is not bonded. Place terminal di[15] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y29' at site IDELAY_X0Y29, Site IOB_X0Y29 is not bonded. Place terminal di[30] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y3' at site IDELAY_X0Y3, Site IOB_X0Y3 is not bonded. Place terminal di[32] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y30' at site IDELAY_X0Y30, Site IOB_X0Y30 is not bonded. Place terminal di[31] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y31' at site IDELAY_X0Y31, Site IOB_X0Y31 is not bonded. Place terminal di[4] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y32' at site IDELAY_X0Y32, Site IOB_X0Y32 is not bonded. Place terminal di[5] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y33' at site IDELAY_X0Y33, Site IOB_X0Y33 is not bonded. Place terminal di[34] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y34' at site IDELAY_X0Y34, Site IOB_X0Y34 is not bonded. Place terminal di[35] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y35' at site IDELAY_X0Y35, Site IOB_X0Y35 is not bonded. Place terminal di[36] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y36' at site IDELAY_X0Y36, Site IOB_X0Y36 is not bonded. Place terminal di[37] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y38' at site IDELAY_X0Y38, Site IOB_X0Y38 is not bonded. Place terminal di[13] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y39' at site IDELAY_X0Y39, Site IOB_X0Y39 is not bonded. Place terminal di[38] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y4' at site IDELAY_X0Y4, Site IOB_X0Y4 is not bonded. Place terminal di[33] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y40' at site IDELAY_X0Y40, Site IOB_X0Y40 is not bonded. Place terminal di[39] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y41' at site IDELAY_X0Y41, Site IOB_X0Y41 is not bonded. Place terminal di[40] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y42' at site IDELAY_X0Y42, Site IOB_X0Y42 is not bonded. Place terminal di[41] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y43' at site IDELAY_X0Y43, Site IOB_X0Y43 is not bonded. Place terminal di[6] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y44' at site IDELAY_X0Y44, Site IOB_X0Y44 is not bonded. Place terminal di[7] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y45' at site IDELAY_X0Y45, Site IOB_X0Y45 is not bonded. Place terminal di[42] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y46' at site IDELAY_X0Y46, Site IOB_X0Y46 is not bonded. Place terminal di[43] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y47' at site IDELAY_X0Y47, Site IOB_X0Y47 is not bonded. Place terminal di[44] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y48' at site IDELAY_X0Y48, Site IOB_X0Y48 is not bonded. Place terminal di[45] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y49' at site IDELAY_X0Y49, Site IOB_X0Y49 is not bonded. Place terminal di[1] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y0' at site IDELAY_X1Y0, Site IOB_X1Y0 is not bonded. Place terminal di[50] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y1' at site IDELAY_X1Y1, Site IOB_X1Y1 is not bonded. Place terminal di[92] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y10' at site IDELAY_X1Y10, Site IOB_X1Y10 is not bonded. Place terminal di[193] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2335] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y11' at site IDELAY_X1Y11, Site IOB_X1Y11 is not bonded. Place terminal di[102] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1243] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y12' at site IDELAY_X1Y12, Site IOB_X1Y12 is not bonded. Place terminal di[103] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1255] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y13' at site IDELAY_X1Y13, Site IOB_X1Y13 is not bonded. Place terminal di[82] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y14' at site IDELAY_X1Y14, Site IOB_X1Y14 is not bonded. Place terminal di[83] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y15' at site IDELAY_X1Y15, Site IOB_X1Y15 is not bonded. Place terminal di[132] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1603] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y16' at site IDELAY_X1Y16, Site IOB_X1Y16 is not bonded. Place terminal di[133] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1615] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y17' at site IDELAY_X1Y17, Site IOB_X1Y17 is not bonded. Place terminal di[134] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1627] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y18' at site IDELAY_X1Y18, Site IOB_X1Y18 is not bonded. Place terminal di[135] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1639] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y19' at site IDELAY_X1Y19, Site IOB_X1Y19 is not bonded. Place terminal di[64] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y2' at site IDELAY_X1Y2, Site IOB_X1Y2 is not bonded. Place terminal di[93] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y20' at site IDELAY_X1Y20, Site IOB_X1Y20 is not bonded. Place terminal di[65] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y21' at site IDELAY_X1Y21, Site IOB_X1Y21 is not bonded. Place terminal di[136] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1651] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y22' at site IDELAY_X1Y22, Site IOB_X1Y22 is not bonded. Place terminal di[137] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1663] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y23' at site IDELAY_X1Y23, Site IOB_X1Y23 is not bonded. Place terminal di[138] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1675] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y24' at site IDELAY_X1Y24, Site IOB_X1Y24 is not bonded. Place terminal di[139] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1687] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y25' at site IDELAY_X1Y25, Site IOB_X1Y25 is not bonded. Place terminal di[140] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1699] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y26' at site IDELAY_X1Y26, Site IOB_X1Y26 is not bonded. Place terminal di[141] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1711] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y27' at site IDELAY_X1Y27, Site IOB_X1Y27 is not bonded. Place terminal di[142] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1723] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y28' at site IDELAY_X1Y28, Site IOB_X1Y28 is not bonded. Place terminal di[143] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1735] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y29' at site IDELAY_X1Y29, Site IOB_X1Y29 is not bonded. Place terminal di[144] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1747] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y3' at site IDELAY_X1Y3, Site IOB_X1Y3 is not bonded. Place terminal di[146] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1771] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y30' at site IDELAY_X1Y30, Site IOB_X1Y30 is not bonded. Place terminal di[145] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1759] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y31' at site IDELAY_X1Y31, Site IOB_X1Y31 is not bonded. Place terminal di[66] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y32' at site IDELAY_X1Y32, Site IOB_X1Y32 is not bonded. Place terminal di[67] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y33' at site IDELAY_X1Y33, Site IOB_X1Y33 is not bonded. Place terminal di[148] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1795] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y34' at site IDELAY_X1Y34, Site IOB_X1Y34 is not bonded. Place terminal di[149] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1807] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y35' at site IDELAY_X1Y35, Site IOB_X1Y35 is not bonded. Place terminal di[150] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1819] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y36' at site IDELAY_X1Y36, Site IOB_X1Y36 is not bonded. Place terminal di[151] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1831] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y37' at site IDELAY_X1Y37, Site IOB_X1Y37 is not bonded. Place terminal di[86] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y38' at site IDELAY_X1Y38, Site IOB_X1Y38 is not bonded. Place terminal di[87] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y39' at site IDELAY_X1Y39, Site IOB_X1Y39 is not bonded. Place terminal di[152] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1843] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y4' at site IDELAY_X1Y4, Site IOB_X1Y4 is not bonded. Place terminal di[147] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1783] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y40' at site IDELAY_X1Y40, Site IOB_X1Y40 is not bonded. Place terminal di[153] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1855] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y41' at site IDELAY_X1Y41, Site IOB_X1Y41 is not bonded. Place terminal di[154] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1867] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y42' at site IDELAY_X1Y42, Site IOB_X1Y42 is not bonded. Place terminal di[155] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1879] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y43' at site IDELAY_X1Y43, Site IOB_X1Y43 is not bonded. Place terminal di[68] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y44' at site IDELAY_X1Y44, Site IOB_X1Y44 is not bonded. Place terminal di[69] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y45' at site IDELAY_X1Y45, Site IOB_X1Y45 is not bonded. Place terminal di[156] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1891] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y46' at site IDELAY_X1Y46, Site IOB_X1Y46 is not bonded. Place terminal di[157] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1903] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y47' at site IDELAY_X1Y47, Site IOB_X1Y47 is not bonded. Place terminal di[158] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1915] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y48' at site IDELAY_X1Y48, Site IOB_X1Y48 is not bonded. Place terminal di[159] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1927] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y49' at site IDELAY_X1Y49, Site IOB_X1Y49 is not bonded. Place terminal di[53] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y5' at site IDELAY_X1Y5, Site IOB_X1Y5 is not bonded. Place terminal di[160] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1939] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y6' at site IDELAY_X1Y6, Site IOB_X1Y6 is not bonded. Place terminal di[161] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1951] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y7' at site IDELAY_X1Y7, Site IOB_X1Y7 is not bonded. Place terminal di[74] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y8' at site IDELAY_X1Y8, Site IOB_X1Y8 is not bonded. Place terminal di[75] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y9' at site IDELAY_X1Y9, Site IOB_X1Y9 is not bonded. Place terminal di[192] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2323] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12888 ; free virtual = 47500 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12910 ; free virtual = 47523 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- 18 Infos, 200 Warnings, 75 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1399.684 ; gain = 316.797 ; free physical = 12914 ; free virtual = 47526 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Looping INT_L_X0Y0 0 IDELAY_X0Y0 IOB_X0Y0 {di[0]} key "IOB_X0Y0" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl" line 75) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:10:27 2019... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 12918 ; free virtual = 47534 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 12919 ; free virtual = 47535 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12936 ; free virtual = 47553 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12946 ; free virtual = 47563 --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 12948 ; free virtual = 47565 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12947 ; free virtual = 47564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12950 ; free virtual = 47568 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12959 ; free virtual = 47578 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 12972 ; free virtual = 47592 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 12976 ; free virtual = 47595 INFO: [Project 1-571] Translating synthesized netlist Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' Makefile:60: recipe for target 'iob_int/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 13252 ; free virtual = 47884 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1404.926 ; gain = 322.039 ; free physical = 13330 ; free virtual = 47962 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1484.961 ; gain = 0.000 ; free physical = 13326 ; free virtual = 47959 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1484.961 ; gain = 0.000 ; free physical = 13326 ; free virtual = 47959 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 13282 ; free virtual = 47896 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 13349 ; free virtual = 47963 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 13350 ; free virtual = 47964 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Placer Task 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 13334 ; free virtual = 47967 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 13342 ; free virtual = 47976 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 13332 ; free virtual = 47966 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 13323 ; free virtual = 47957 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 13319 ; free virtual = 47952 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 13280 ; free virtual = 47894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 13279 ; free virtual = 47893 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 13185 ; free virtual = 47798 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1583c4629 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 13180 ; free virtual = 47794 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1416.590 ; gain = 333.695 ; free physical = 13182 ; free virtual = 47795 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.621 ; gain = 0.000 ; free physical = 13050 ; free virtual = 47664 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.621 ; gain = 0.000 ; free physical = 13045 ; free virtual = 47659 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 12872 ; free virtual = 47486 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 12746 ; free virtual = 47360 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 12733 ; free virtual = 47347 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 12647 ; free virtual = 47261 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 12632 ; free virtual = 47246 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 12660 ; free virtual = 47274 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12556 ; free virtual = 47170 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12484 ; free virtual = 47098 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12482 ; free virtual = 47096 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12472 ; free virtual = 47086 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12470 ; free virtual = 47084 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12468 ; free virtual = 47082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12463 ; free virtual = 47077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12462 ; free virtual = 47076 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12460 ; free virtual = 47074 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 12461 ; free virtual = 47075 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 11791 ; free virtual = 46405 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11738 ; free virtual = 46352 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11730 ; free virtual = 46344 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11729 ; free virtual = 46343 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11728 ; free virtual = 46342 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11727 ; free virtual = 46341 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 11725 ; free virtual = 46339 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 11724 ; free virtual = 46338 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 11110 ; free virtual = 45724 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 11010 ; free virtual = 45624 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10985 ; free virtual = 45599 Phase 1.3 Build Placer Netlist Model Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10959 ; free virtual = 45573 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10958 ; free virtual = 45572 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10956 ; free virtual = 45570 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10955 ; free virtual = 45569 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10952 ; free virtual = 45566 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 10952 ; free virtual = 45566 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 10743 ; free virtual = 45357 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 10693 ; free virtual = 45307 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.449 ; gain = 0.000 ; free physical = 10656 ; free virtual = 45270 Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 10643 ; free virtual = 45257 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 10598 ; free virtual = 45212 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 10627 ; free virtual = 45241 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 10622 ; free virtual = 45236 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 10621 ; free virtual = 45234 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 10566 ; free virtual = 45179 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.492 ; gain = 454.531 ; free physical = 10349 ; free virtual = 44963 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.492 ; gain = 454.531 ; free physical = 10309 ; free virtual = 44923 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.492 ; gain = 454.531 ; free physical = 10304 ; free virtual = 44918 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.492 ; gain = 454.531 ; free physical = 10301 ; free virtual = 44915 Phase 2 Global Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.445 ; gain = 0.000 ; free physical = 10075 ; free virtual = 44689 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 10077 ; free virtual = 44691 Starting Routing Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5764 Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 10077 ; free virtual = 44691 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 10076 ; free virtual = 44690 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 10076 ; free virtual = 44690 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 10076 ; free virtual = 44690 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 10076 ; free virtual = 44690 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 10077 ; free virtual = 44691 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 10077 ; free virtual = 44691 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 10039 ; free virtual = 44653 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 10041 ; free virtual = 44655 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 10039 ; free virtual = 44653 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 10035 ; free virtual = 44649 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 10031 ; free virtual = 44645 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 10001 ; free virtual = 44615 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.488 ; gain = 581.562 ; free physical = 10001 ; free virtual = 44615 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b00cead Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9948 ; free virtual = 44562 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1a2533493 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9937 ; free virtual = 44551 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2533493 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9932 ; free virtual = 44546 Phase 1 Placer Initialization | Checksum: 1a2533493 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9931 ; free virtual = 44545 Phase 2 Global Placement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 6413 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9499 ; free virtual = 44113 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9491 ; free virtual = 44105 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9486 ; free virtual = 44100 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9479 ; free virtual = 44093 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9479 ; free virtual = 44093 Phase 3.5 Small Shape Detail Placement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.109 ; gain = 0.000 ; free physical = 9441 ; free virtual = 44055 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9442 ; free virtual = 44056 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9442 ; free virtual = 44056 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9442 ; free virtual = 44056 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9441 ; free virtual = 44055 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9441 ; free virtual = 44055 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9439 ; free virtual = 44053 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9439 ; free virtual = 44053 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9439 ; free virtual = 44053 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9439 ; free virtual = 44053 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.539 ; gain = 550.578 ; free physical = 9451 ; free virtual = 44065 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.539 ; gain = 614.609 ; free physical = 9451 ; free virtual = 44065 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.152 ; gain = 510.531 ; free physical = 9401 ; free virtual = 44015 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 510.531 ; free physical = 9390 ; free virtual = 44004 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 510.531 ; free physical = 9386 ; free virtual = 44000 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 510.531 ; free physical = 9381 ; free virtual = 43996 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 510.531 ; free physical = 9380 ; free virtual = 43994 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.152 ; gain = 510.531 ; free physical = 9380 ; free virtual = 43994 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.152 ; gain = 576.562 ; free physical = 9379 ; free virtual = 43993 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9351 ; free virtual = 43965 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9338 ; free virtual = 43952 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d4686e25 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9342 ; free virtual = 43956 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ae434bf0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9329 ; free virtual = 43943 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 177f7ac55 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9326 ; free virtual = 43940 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9307 ; free virtual = 43922 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9307 ; free virtual = 43921 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9306 ; free virtual = 43920 Phase 3 Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9309 ; free virtual = 43923 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9304 ; free virtual = 43918 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9303 ; free virtual = 43917 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9303 ; free virtual = 43917 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9311 ; free virtual = 43925 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9311 ; free virtual = 43925 Ending Placer Task | Checksum: 1c0d5e9dc Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 9322 ; free virtual = 43936 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 659.605 ; free physical = 9322 ; free virtual = 43936 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: dc3640d2 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 8901 ; free virtual = 43516 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 8646 ; free virtual = 43260 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 8667 ; free virtual = 43282 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 8662 ; free virtual = 43277 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 8657 ; free virtual = 43271 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8479 ; free virtual = 43093 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 8319 ; free virtual = 42933 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8252 ; free virtual = 42867 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8211 ; free virtual = 42826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8208 ; free virtual = 42822 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8207 ; free virtual = 42821 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 8090 ; free virtual = 42704 Phase 1.3 Build Placer Netlist Model Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 7845 ; free virtual = 42459 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 7821 ; free virtual = 42436 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7819 ; free virtual = 42434 Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 7819 ; free virtual = 42434 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 7817 ; free virtual = 42432 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 7813 ; free virtual = 42428 Phase 2 Global Placement 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 7843 ; free virtual = 42458 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7826 ; free virtual = 42441 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7826 ; free virtual = 42441 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7826 ; free virtual = 42441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7826 ; free virtual = 42441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7826 ; free virtual = 42440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7826 ; free virtual = 42440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7825 ; free virtual = 42439 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 7825 ; free virtual = 42440 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7825 ; free virtual = 42440 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 7745 ; free virtual = 42359 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 7744 ; free virtual = 42358 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7744 ; free virtual = 42358 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1551.859 ; gain = 0.000 ; free physical = 7728 ; free virtual = 42343 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.55 . Memory (MB): peak = 1551.859 ; gain = 0.000 ; free physical = 7726 ; free virtual = 42341 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7727 ; free virtual = 42342 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7724 ; free virtual = 42339 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7721 ; free virtual = 42335 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7720 ; free virtual = 42335 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7720 ; free virtual = 42334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7720 ; free virtual = 42334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7720 ; free virtual = 42334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7719 ; free virtual = 42334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7719 ; free virtual = 42334 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 7719 ; free virtual = 42333 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 7720 ; free virtual = 42335 INFO: [Project 1-571] Translating synthesized netlist Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7702 ; free virtual = 42316 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7704 ; free virtual = 42318 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7687 ; free virtual = 42302 Phase 3.5 Small Shape Detail Placement INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1396.680 ; gain = 313.797 ; free physical = 7668 ; free virtual = 42282 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.711 ; gain = 0.000 ; free physical = 7651 ; free virtual = 42266 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1460.711 ; gain = 0.000 ; free physical = 7651 ; free virtual = 42266 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7651 ; free virtual = 42266 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7648 ; free virtual = 42262 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7644 ; free virtual = 42258 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7640 ; free virtual = 42255 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7592 ; free virtual = 42207 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7575 ; free virtual = 42190 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7563 ; free virtual = 42177 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7550 ; free virtual = 42165 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 7574 ; free virtual = 42189 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7574 ; free virtual = 42189 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 542.246 ; free physical = 7600 ; free virtual = 42214 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.195 ; gain = 623.949 ; free physical = 7599 ; free virtual = 42213 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 7569 ; free virtual = 42184 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 7569 ; free virtual = 42183 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.930 ; gain = 119.668 ; free physical = 7349 ; free virtual = 41964 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 7313 ; free virtual = 41928 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 7310 ; free virtual = 41925 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7273 ; free virtual = 41887 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7258 ; free virtual = 41873 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7258 ; free virtual = 41873 Phase 4 Rip-up And Reroute | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7258 ; free virtual = 41873 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7258 ; free virtual = 41873 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7258 ; free virtual = 41873 Phase 6 Post Hold Fix | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 130.711 ; free physical = 7258 ; free virtual = 41873 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1439f5939 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7255 ; free virtual = 41870 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1439f5939 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 7254 ; free virtual = 41869 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1439f5939 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 7254 ; free virtual = 41869 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.973 ; gain = 133.711 ; free physical = 7287 ; free virtual = 41902 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2108.762 ; gain = 204.516 ; free physical = 7287 ; free virtual = 41902 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2108.762 ; gain = 0.000 ; free physical = 7282 ; free virtual = 41898 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2054.934 ; gain = 121.668 ; free physical = 7145 ; free virtual = 41760 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2059.922 ; gain = 126.656 ; free physical = 7079 ; free virtual = 41694 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2059.922 ; gain = 126.656 ; free physical = 7078 ; free virtual = 41693 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e90f676 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6932 ; free virtual = 41547 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.172 ; gain = 43.668 ; free physical = 6930 ; free virtual = 41545 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 6900 ; free virtual = 41515 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 6902 ; free virtual = 41517 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6882 ; free virtual = 41497 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6872 ; free virtual = 41487 Phase 4 Rip-up And Reroute | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6872 ; free virtual = 41487 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6872 ; free virtual = 41487 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6872 ; free virtual = 41487 Phase 6 Post Hold Fix | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6872 ; free virtual = 41487 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0INFO: [Timing 38-35] Done setting XDC timing constraints. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 6864 ; free virtual = 41479 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 6861 ; free virtual = 41476 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 6861 ; free virtual = 41476 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 135.711 ; free physical = 6890 ; free virtual = 41505 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2107.766 ; gain = 206.516 ; free physical = 6887 ; free virtual = 41502 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.465 ; gain = 60.961 ; free physical = 6846 ; free virtual = 41461 Phase 3 Initial Routing Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2107.766 ; gain = 0.000 ; free physical = 6866 ; free virtual = 41483 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: d50581c6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2057.926 ; gain = 93.668 ; free physical = 6898 ; free virtual = 41514 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6841 ; free virtual = 41456 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d50581c6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.914 ; gain = 97.656 ; free physical = 6845 ; free virtual = 41460 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d50581c6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.914 ; gain = 97.656 ; free physical = 6847 ; free virtual = 41462 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6830 ; free virtual = 41445 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6824 ; free virtual = 41439 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6808 ; free virtual = 41423 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6800 ; free virtual = 41415 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6771 ; free virtual = 41386 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6752 ; free virtual = 41367 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 6745 ; free virtual = 41360 Phase 9 Depositing Routes Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6711 ; free virtual = 41326 Phase 3 Initial Routing Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 6710 ; free virtual = 41325 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 6744 ; free virtual = 41359 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2127.254 ; gain = 136.766 ; free physical = 6747 ; free virtual = 41362 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1963.348 ; gain = 0.000 ; free physical = 6743 ; free virtual = 41359 Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6797 ; free virtual = 41412 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6795 ; free virtual = 41410 Phase 4 Rip-up And Reroute | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6794 ; free virtual = 41410 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6794 ; free virtual = 41410 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6794 ; free virtual = 41410 Phase 6 Post Hold Fix | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6794 ; free virtual = 41410 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 6770 ; free virtual = 41386 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 6768 ; free virtual = 41384 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 6764 ; free virtual = 41380 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 6796 ; free virtual = 41412 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2110.758 ; gain = 178.516 ; free physical = 6794 ; free virtual = 41410 Running DRC as a precondition to command write_bitstream Writing XDEF routing. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 6777 ; free virtual = 41396 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2110.758 ; gain = 0.000 ; free physical = 6753 ; free virtual = 41373 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2063.172 ; gain = 44.668 ; free physical = 6593 ; free virtual = 41209 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.160 ; gain = 50.656 ; free physical = 6540 ; free virtual = 41156 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.160 ; gain = 50.656 ; free physical = 6544 ; free virtual = 41160 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.215 ; gain = 60.711 ; free physical = 6563 ; free virtual = 41179 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6518 ; free virtual = 41134 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2051.391 ; gain = 499.531 ; free physical = 6520 ; free virtual = 41136 Phase 1.3 Build Placer Netlist Model Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6518 ; free virtual = 41134 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6519 ; free virtual = 41135 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6520 ; free virtual = 41136 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6517 ; free virtual = 41133 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6515 ; free virtual = 41131 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2081.215 ; gain = 62.711 ; free physical = 6415 ; free virtual = 41031 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2083.215 ; gain = 64.711 ; free physical = 6412 ; free virtual = 41028 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2083.215 ; gain = 64.711 ; free physical = 6370 ; free virtual = 40986 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2083.215 ; gain = 64.711 ; free physical = 6403 ; free virtual = 41019 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2122.004 ; gain = 135.516 ; free physical = 6401 ; free virtual = 41017 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2122.004 ; gain = 0.000 ; free physical = 6353 ; free virtual = 40971 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.199 ; gain = 0.000 ; free physical = 6336 ; free virtual = 40954 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.242 ; gain = 443.531 ; free physical = 6305 ; free virtual = 40921 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.242 ; gain = 443.531 ; free physical = 6307 ; free virtual = 40923 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.242 ; gain = 443.531 ; free physical = 6307 ; free virtual = 40923 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.242 ; gain = 443.531 ; free physical = 6307 ; free virtual = 40923 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.242 ; gain = 443.531 ; free physical = 6307 ; free virtual = 40923 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.242 ; gain = 443.531 ; free physical = 6311 ; free virtual = 40927 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1904.242 ; gain = 507.562 ; free physical = 6311 ; free virtual = 40927 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.836 ; gain = 42.668 ; free physical = 6107 ; free virtual = 40723 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.824 ; gain = 48.656 ; free physical = 5980 ; free virtual = 40597 Phase 2.2 Pre Route Cleanup Loading data files... Phase 2.2 Pre Route Cleanup | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.824 ; gain = 48.656 ; free physical = 5982 ; free virtual = 40598 Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.180 ; gain = 33.641 ; free physical = 5824 ; free virtual = 40440 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2075.168 ; gain = 39.629 ; free physical = 5740 ; free virtual = 40357 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2075.168 ; gain = 39.629 ; free physical = 5740 ; free virtual = 40356 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.129 ; gain = 60.961 ; free physical = 5699 ; free virtual = 40315 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1815.207 ; gain = 0.000 ; free physical = 5632 ; free virtual = 40248 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.129 ; gain = 61.961 ; free physical = 5673 ; free virtual = 40289 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.129 ; gain = 61.961 ; free physical = 5674 ; free virtual = 40290 Phase 4 Rip-up And Reroute | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.129 ; gain = 61.961 ; free physical = 5669 ; free virtual = 40286 Phase 5 Delay and Skew Optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5669 ; free virtual = 40285 Phase 3 Initial Routing Phase 5 Delay and Skew Optimization | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.129 ; gain = 61.961 ; free physical = 5669 ; free virtual = 40285 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.129 ; gain = 61.961 ; free physical = 5663 ; free virtual = 40280 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 5662 ; free virtual = 40279 Phase 1.3 Build Placer Netlist Model Phase 6 Post Hold Fix | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.129 ; gain = 61.961 ; free physical = 5660 ; free virtual = 40277 Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 5651 ; free virtual = 40268 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 5651 ; free virtual = 40268 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 5651 ; free virtual = 40267 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 5650 ; free virtual = 40267 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 7 Route finalize Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 5643 ; free virtual = 40260 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1903.250 ; gain = 505.562 ; free physical = 5639 ; free virtual = 40256 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.129 ; gain = 62.961 ; free physical = 5593 ; free virtual = 40210 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.129 ; gain = 64.961 ; free physical = 5575 ; free virtual = 40192 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.129 ; gain = 65.961 ; free physical = 5541 ; free virtual = 40157 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.129 ; gain = 65.961 ; free physical = 5582 ; free virtual = 40199 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.918 ; gain = 136.766 ; free physical = 5576 ; free virtual = 40192 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5577 ; free virtual = 40194 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.391 ; gain = 499.531 ; free physical = 5578 ; free virtual = 40194 Phase 1.4 Constrain Clocks/Macros Loading data files... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5576 ; free virtual = 40193 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5576 ; free virtual = 40193 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5575 ; free virtual = 40192 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5575 ; free virtual = 40192 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5575 ; free virtual = 40192 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.391 ; gain = 499.531 ; free physical = 5571 ; free virtual = 40188 Writing placer database... Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5585 ; free virtual = 40202 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5590 ; free virtual = 40207 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5592 ; free virtual = 40209 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2096.223 ; gain = 60.684 ; free physical = 5633 ; free virtual = 40249 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2135.012 ; gain = 99.473 ; free physical = 5635 ; free virtual = 40252 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.391 ; gain = 499.531 ; free physical = 5647 ; free virtual = 40264 Phase 2 Final Placement Cleanup Writing XDEF routing. Loading data files... Writing XDEF routing logical nets. Writing XDEF routing special nets. Writing placer database... Writing XDEF routing. Write XDEF Complete: Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2129.918 ; gain = 0.000 ; free physical = 5627 ; free virtual = 40247 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2135.012 ; gain = 0.000 ; free physical = 5623 ; free virtual = 40245 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.391 ; gain = 499.531 ; free physical = 5609 ; free virtual = 40230 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.391 ; gain = 499.531 ; free physical = 5543 ; free virtual = 40161 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2051.391 ; gain = 574.562 ; free physical = 5534 ; free virtual = 40151 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 5349 ; free virtual = 39966 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 5311 ; free virtual = 39929 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 5312 ; free virtual = 39929 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b9dafcfc Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5191 ; free virtual = 39809 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5168 ; free virtual = 39786 Loading data files... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5171 ; free virtual = 39788 Phase 4 Rip-up And Reroute | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5172 ; free virtual = 39789 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5176 ; free virtual = 39793 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5179 ; free virtual = 39796 Phase 6 Post Hold Fix | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5180 ; free virtual = 39797 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5169 ; free virtual = 39786 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5168 ; free virtual = 39785 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5169 ; free virtual = 39786 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.230 ; gain = 16.688 ; free physical = 5205 ; free virtual = 39823 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2140.020 ; gain = 55.477 ; free physical = 5206 ; free virtual = 39824 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Writing placer database... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 5198 ; free virtual = 39817 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading route data... Processing options... Creating bitmap... Loading data files... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Loading site data... Loading route data... Processing options... Creating bitmap... Loading data files... Creating bitstream... Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:11:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 2451.867 ; gain = 343.105 ; free physical = 3945 ; free virtual = 38572 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:00 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2451.871 ; gain = 344.105 ; free physical = 5157 ; free virtual = 39787 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:01 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:04 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2453.863 ; gain = 343.105 ; free physical = 5930 ; free virtual = 40564 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:04 2019... Creating bitstream... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 Creating bitstream... Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2471.359 ; gain = 344.105 ; free physical = 7274 ; free virtual = 41912 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:08 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2466.117 ; gain = 331.105 ; free physical = 8564 ; free virtual = 43206 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:12 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Bitstream size: 4243411 bytes Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.957 ; gain = 37.762 ; free physical = 9731 ; free virtual = 44373 Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints touch build/specimen_001/OK Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2134.945 ; gain = 43.750 ; free physical = 9638 ; free virtual = 44280 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2134.945 ; gain = 43.750 ; free physical = 9635 ; free virtual = 44277 GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_002 Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9607 ; free virtual = 44249 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9657 ; free virtual = 44299 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9658 ; free virtual = 44300 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9658 ; free virtual = 44300 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9658 ; free virtual = 44300 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9658 ; free virtual = 44300 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9658 ; free virtual = 44300 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9653 ; free virtual = 44295 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9652 ; free virtual = 44294 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9651 ; free virtual = 44293 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 9686 ; free virtual = 44328 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:53 . Memory (MB): peak = 2193.789 ; gain = 102.594 ; free physical = 9686 ; free virtual = 44328 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing bitstream ./design.bit... 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2460.109 ; gain = 338.105 ; free physical = 9670 ; free virtual = 44320 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:15 2019... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.789 ; gain = 0.000 ; free physical = 11079 ; free virtual = 45753 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.125 ; gain = 334.105 ; free physical = 11075 ; free virtual = 45727 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:19 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2470.023 ; gain = 340.105 ; free physical = 11072 ; free virtual = 45724 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:19 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9300 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9301 Phase 1 Build RT Design | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.926 ; gain = 119.668 ; free physical = 12735 ; free virtual = 47390 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.914 ; gain = 124.656 ; free physical = 12695 ; free virtual = 47350 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.914 ; gain = 124.656 ; free physical = 12695 ; free virtual = 47350 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12621 ; free virtual = 47276 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12586 ; free virtual = 47241 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12553 ; free virtual = 47208 Phase 4 Rip-up And Reroute | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12553 ; free virtual = 47208 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12552 ; free virtual = 47207 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12552 ; free virtual = 47207 Phase 6 Post Hold Fix | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.969 ; gain = 130.711 ; free physical = 12552 ; free virtual = 47206 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c45c954e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.969 ; gain = 131.711 ; free physical = 12510 ; free virtual = 47165 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c45c954e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.969 ; gain = 133.711 ; free physical = 12508 ; free virtual = 47163 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c45c954e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.969 ; gain = 133.711 ; free physical = 12508 ; free virtual = 47162 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.969 ; gain = 133.711 ; free physical = 12538 ; free virtual = 47193 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2108.758 ; gain = 204.516 ; free physical = 12537 ; free virtual = 47192 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2108.758 ; gain = 0.000 ; free physical = 12588 ; free virtual = 47244 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9388 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2054.934 ; gain = 119.668 ; free physical = 12313 ; free virtual = 46968 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 125.656 ; free physical = 12256 ; free virtual = 46911 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 125.656 ; free physical = 12255 ; free virtual = 46911 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1481dbb17 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12245 ; free virtual = 46900 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12185 ; free virtual = 46840 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12178 ; free virtual = 46833 Phase 4 Rip-up And Reroute | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12178 ; free virtual = 46833 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12177 ; free virtual = 46832 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12176 ; free virtual = 46831 Phase 6 Post Hold Fix | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 12176 ; free virtual = 46831 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 132.711 ; free physical = 12173 ; free virtual = 46828 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 134.711 ; free physical = 12172 ; free virtual = 46827 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 134.711 ; free physical = 12172 ; free virtual = 46827 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 134.711 ; free physical = 12204 ; free virtual = 46859 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2108.766 ; gain = 205.516 ; free physical = 12206 ; free virtual = 46861 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 12169 ; free virtual = 46826 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9436 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 11717 ; free virtual = 46372 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11787 ; free virtual = 46442 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: e91ff6d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2135.074 ; gain = 51.668 ; free physical = 11762 ; free virtual = 46417 Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e91ff6d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.062 ; gain = 60.656 ; free physical = 11697 ; free virtual = 46352 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e91ff6d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.062 ; gain = 60.656 ; free physical = 11690 ; free virtual = 46345 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9487 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11531 ; free virtual = 46186 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Loading data files... Phase 3 Initial Routing | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11495 ; free virtual = 46150 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11506 ; free virtual = 46163 Phase 4 Rip-up And Reroute | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11506 ; free virtual = 46162 Phase 5 Delay and Skew Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] Phase 5 Delay and Skew Optimization | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11507 ; free virtual = 46164 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 11510 ; free virtual = 46166 --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: 18fae605e Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11513 ; free virtual = 46169 Phase 6 Post Hold Fix | Checksum: 18fae605e Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11522 ; free virtual = 46178 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11526 ; free virtual = 46182 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 11539 ; free virtual = 46195 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 11539 ; free virtual = 46195 --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 18fae605e Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11544 ; free virtual = 46200 Phase 8 Verifying routed nets INFO: Launching helper process for spawning children vivado processes Verification completed successfully --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11542 ; free virtual = 46198 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 9530 --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11541 ; free virtual = 46197 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11542 ; free virtual = 46198 --------------------------------------------------------------------------------- Phase 8 Verifying routed nets | Checksum: 18fae605e Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11542 ; free virtual = 46198 Phase 9 Depositing Routes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 11537 ; free virtual = 46193 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Phase 9 Depositing Routes | Checksum: 18fae605e Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11474 ; free virtual = 46130 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.367 ; gain = 94.961 ; free physical = 11509 ; free virtual = 46165 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 2217.156 ; gain = 165.766 ; free physical = 11508 ; free virtual = 46164 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11446 ; free virtual = 46102 --------------------------------------------------------------------------------- Writing placer database... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11165 ; free virtual = 45838 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11139 ; free virtual = 45814 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11139 ; free virtual = 45814 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11132 ; free virtual = 45808 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11135 ; free virtual = 45818 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2217.156 ; gain = 0.000 ; free physical = 11312 ; free virtual = 45999 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11152 ; free virtual = 45816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11118 ; free virtual = 45782 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11132 ; free virtual = 45795 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11122 ; free virtual = 45786 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 9597 INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9652 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 2531.895 ; gain = 338.105 ; free physical = 10868 ; free virtual = 45531 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:42 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10887 ; free virtual = 45551 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 11700 ; free virtual = 46363 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Config size: 1060815 words --------------------------------------------------------------------------------- Number of configuration frames: 9996 Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 11813 ; free virtual = 46476 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11797 ; free virtual = 46460 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11796 ; free virtual = 46459 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11784 ; free virtual = 46447 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11767 ; free virtual = 46430 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11563 ; free virtual = 46230 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11568 ; free virtual = 46235 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11586 ; free virtual = 46253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11588 ; free virtual = 46255 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11590 ; free virtual = 46257 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11592 ; free virtual = 46259 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11596 ; free virtual = 46263 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11601 ; free virtual = 46268 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11604 ; free virtual = 46271 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 11605 ; free virtual = 46272 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 11585 ; free virtual = 46252 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11612 ; free virtual = 46279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11614 ; free virtual = 46281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11616 ; free virtual = 46283 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11619 ; free virtual = 46286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11621 ; free virtual = 46288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11622 ; free virtual = 46289 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000001 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11631 ; free virtual = 46298 INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11632 ; free virtual = 46299 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11820 ; free virtual = 46488 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11887 ; free virtual = 46556 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 11880 ; free virtual = 46548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1205.949 ; gain = 110.508 ; free physical = 11865 ; free virtual = 46533 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... INFO: [Project 1-570] Preparing netlist for logic optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 11707 ; free virtual = 46376 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] No constraint files found. WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 11692 ; free virtual = 46361 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] Report RTL Partitions: WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] --------------------------------------------------------------------------------- Start Technology Mapping WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11683 ; free virtual = 46352 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Start Final Netlist Cleanup Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11682 ; free virtual = 46351 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11677 ; free virtual = 46346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11677 ; free virtual = 46346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11676 ; free virtual = 46345 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11634 ; free virtual = 46303 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11633 ; free virtual = 46302 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11632 ; free virtual = 46301 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11631 ; free virtual = 46300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11631 ; free virtual = 46300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11629 ; free virtual = 46298 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11628 ; free virtual = 46297 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 11625 ; free virtual = 46295 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 11626 ; free virtual = 46295 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11493 ; free virtual = 46162 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11473 ; free virtual = 46142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11460 ; free virtual = 46130 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2451.863 ; gain = 343.105 ; free physical = 11441 ; free virtual = 46114 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:48 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 11531 ; free virtual = 46204 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Bitstream size: 4243411 bytes Config size: 1060815 words Starting Placer Task Number of configuration frames: 9996 DONE INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 12758 ; free virtual = 47431 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 12757 ; free virtual = 47430 touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12729 ; free virtual = 47402 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12727 ; free virtual = 47400 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12718 ; free virtual = 47392 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12713 ; free virtual = 47386 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12709 ; free virtual = 47382 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12706 ; free virtual = 47379 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12703 ; free virtual = 47376 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12699 ; free virtual = 47372 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 12695 ; free virtual = 47368 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 12662 ; free virtual = 47335 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 12655 ; free virtual = 47328 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 12523 ; free virtual = 47197 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading data files... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 12462 ; free virtual = 47136 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 12448 ; free virtual = 47122 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1398.684 ; gain = 315.797 ; free physical = 12470 ; free virtual = 47144 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1847] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1931] Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [DRC 23-27] Running DRC with 8 threads Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:16] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 12460 ; free virtual = 47134 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:12:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2450.871 ; gain = 342.105 ; free physical = 12458 ; free virtual = 47132 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:12:51 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 12463 ; free virtual = 47138 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 12465 ; free virtual = 47140 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 13357 ; free virtual = 48032 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ Bitstream size: 4243411 bytes | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:247] touch build/specimen_003/OK WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:395] GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5061] No constraint files found. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5144] --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5393] Starting Placer Task WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 13306 ; free virtual = 47981 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 13303 ; free virtual = 47977 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.918 ; gain = 232.477 ; free physical = 13288 ; free virtual = 47962 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.918 ; gain = 232.477 ; free physical = 13208 ; free virtual = 47882 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13166 ; free virtual = 47840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 13177 ; free virtual = 47852 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 13181 ; free virtual = 47861 --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1398.688 ; gain = 315.797 ; free physical = 13180 ; free virtual = 47861 --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 13177 ; free virtual = 47857 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13163 ; free virtual = 47838 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13159 ; free virtual = 47834 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13157 ; free virtual = 47833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13157 ; free virtual = 47832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13155 ; free virtual = 47831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13155 ; free virtual = 47830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13154 ; free virtual = 47830 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.934 ; gain = 242.492 ; free physical = 13152 ; free virtual = 47827 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13153 ; free virtual = 47828 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 13117 ; free virtual = 47793 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 13100 ; free virtual = 47775 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 13086 ; free virtual = 47761 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 13070 ; free virtual = 47744 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 13037 ; free virtual = 47711 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 13037 ; free virtual = 47711 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12969 ; free virtual = 47644 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12967 ; free virtual = 47642 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12963 ; free virtual = 47638 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12962 ; free virtual = 47637 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12961 ; free virtual = 47636 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12958 ; free virtual = 47633 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12958 ; free virtual = 47632 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 12949 ; free virtual = 47624 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 12931 ; free virtual = 47606 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1420.934 ; gain = 338.047 ; free physical = 12612 ; free virtual = 47287 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 12532 ; free virtual = 47207 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 12498 ; free virtual = 47173 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12487 ; free virtual = 47162 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1484.965 ; gain = 0.000 ; free physical = 12465 ; free virtual = 47140 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1484.965 ; gain = 0.000 ; free physical = 12465 ; free virtual = 47140 Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12373 ; free virtual = 47048 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12372 ; free virtual = 47047 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12369 ; free virtual = 47044 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12368 ; free virtual = 47043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12367 ; free virtual = 47042 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12366 ; free virtual = 47041 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12365 ; free virtual = 47040 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.496 ; free physical = 12355 ; free virtual = 47030 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.953 ; gain = 246.496 ; free physical = 12352 ; free virtual = 47027 INFO: [Project 1-571] Translating synthesized netlist Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 12249 ; free virtual = 46924 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 12184 ; free virtual = 46859 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 12165 ; free virtual = 46840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12230 ; free virtual = 46905 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 12223 ; free virtual = 46898 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 12222 ; free virtual = 46897 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12202 ; free virtual = 46877 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12200 ; free virtual = 46875 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12198 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12198 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12198 ; free virtual = 46873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12197 ; free virtual = 46872 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12197 ; free virtual = 46872 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12194 ; free virtual = 46869 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12195 ; free virtual = 46870 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10017 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.945 ; gain = 342.055 ; free physical = 11707 ; free virtual = 46382 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 11228 ; free virtual = 45903 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11189 ; free virtual = 45864 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11187 ; free virtual = 45862 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11187 ; free virtual = 45862 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11187 ; free virtual = 45862 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11187 ; free virtual = 45862 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11188 ; free virtual = 45863 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 11188 ; free virtual = 45863 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.977 ; gain = 0.000 ; free physical = 11210 ; free virtual = 45885 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d7f8aeb2 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1488.977 ; gain = 0.000 ; free physical = 11202 ; free virtual = 45877 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1902.441 ; gain = 0.000 ; free physical = 11129 ; free virtual = 45804 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 11047 ; free virtual = 45722 Phase 1.3 Build Placer Netlist Model Creating bitstream... Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 11034 ; free virtual = 45709 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 11028 ; free virtual = 45703 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 10999 ; free virtual = 45675 Phase 2 Final Placement Cleanup INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 10983 ; free virtual = 45658 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 10963 ; free virtual = 45638 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.484 ; gain = 583.562 ; free physical = 10960 ; free virtual = 45635 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10134 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1842.203 ; gain = 0.000 ; free physical = 10615 ; free virtual = 45290 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 10609 ; free virtual = 45284 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.207 ; gain = 0.000 ; free physical = 10415 ; free virtual = 45090 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 10392 ; free virtual = 45067 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 10392 ; free virtual = 45067 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 10392 ; free virtual = 45067 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 10392 ; free virtual = 45067 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 10392 ; free virtual = 45067 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 10393 ; free virtual = 45068 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 531.562 ; free physical = 10392 ; free virtual = 45067 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing bitstream ./design.bit... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 10374 ; free virtual = 45051 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 10363 ; free virtual = 45041 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 10605 ; free virtual = 45284 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 10626 ; free virtual = 45305 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 10649 ; free virtual = 45329 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 10651 ; free virtual = 45330 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb INFO: [Vivado 12-1842] Bitgen Completed Successfully. Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 10656 ; free virtual = 45335 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 10658 ; free virtual = 45337 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 532.562 ; free physical = 10658 ; free virtual = 45337 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10257 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10544 ; free virtual = 45223 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:13:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:40 . Memory (MB): peak = 2605.277 ; gain = 388.121 ; free physical = 10373 ; free virtual = 45053 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:13:19 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:16] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.453 ; gain = 0.000 ; free physical = 10933 ; free virtual = 45618 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10790 ; free virtual = 45475 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10799 ; free virtual = 45484 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10803 ; free virtual = 45488 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1939.496 ; gain = 454.531 ; free physical = 10803 ; free virtual = 45488 Phase 2 Global Placement --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10712 ; free virtual = 45397 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10719 ; free virtual = 45410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10463 ; free virtual = 45148 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 10461 ; free virtual = 45146 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10455 ; free virtual = 45141 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 10411 ; free virtual = 45096 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10368 ; free virtual = 45053 Phase 1.3 Build Placer Netlist Model WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10359 ; free virtual = 45044 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10352 ; free virtual = 45037 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10350 ; free virtual = 45035 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10348 ; free virtual = 45034 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10348 ; free virtual = 45033 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 10347 ; free virtual = 45033 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10227 ; free virtual = 44912 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10229 ; free virtual = 44914 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10229 ; free virtual = 44915 Phase 3.3 Area Swap Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10233 ; free virtual = 44918 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10233 ; free virtual = 44918 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 10276 ; free virtual = 44962 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 10270 ; free virtual = 44956 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 10269 ; free virtual = 44955 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 10269 ; free virtual = 44955 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10264 ; free virtual = 44949 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10263 ; free virtual = 44949 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10263 ; free virtual = 44949 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.539 ; gain = 542.574 ; free physical = 10277 ; free virtual = 44962 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2027.539 ; gain = 606.605 ; free physical = 10275 ; free virtual = 44961 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10143 ; free virtual = 44829 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9841 ; free virtual = 44528 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.465 ; gain = 0.000 ; free physical = 9860 ; free virtual = 44546 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9830 ; free virtual = 44517 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 9829 ; free virtual = 44515 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ddcd7ec8 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.508 ; gain = 507.531 ; free physical = 9814 ; free virtual = 44500 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2751fe4ae Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.508 ; gain = 507.531 ; free physical = 9802 ; free virtual = 44489 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2751fe4ae Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.508 ; gain = 507.531 ; free physical = 9801 ; free virtual = 44487 Phase 1 Placer Initialization | Checksum: 2751fe4ae Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.508 ; gain = 507.531 ; free physical = 9799 ; free virtual = 44485 Phase 2 Global Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9332 ; free virtual = 44018 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9278 ; free virtual = 43964 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 9256 ; free virtual = 43942 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 9273 ; free virtual = 43959 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9232 ; free virtual = 43918 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9231 ; free virtual = 43917 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9230 ; free virtual = 43917 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9228 ; free virtual = 43917 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9220 ; free virtual = 43912 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9223 ; free virtual = 43909 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 2 Global Placement | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9226 ; free virtual = 43912 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9225 ; free virtual = 43911 Phase 3.2 Commit Most Macros & LUTRAMs Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9226 ; free virtual = 43912 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 9226 ; free virtual = 43912 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 20d0b931e Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9225 ; free virtual = 43911 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1e6e670e9 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9209 ; free virtual = 43896 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b09ad14e Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9208 ; free virtual = 43894 Phase 3.5 Small Shape Detail Placement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9206 ; free virtual = 43892 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9194 ; free virtual = 43880 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9188 ; free virtual = 43874 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9117 ; free virtual = 43803 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9117 ; free virtual = 43803 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9114 ; free virtual = 43800 Phase 3 Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9113 ; free virtual = 43799 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9106 ; free virtual = 43792 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9140 ; free virtual = 43826 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9134 ; free virtual = 43820 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9129 ; free virtual = 43815 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9127 ; free virtual = 43813 --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9127 ; free virtual = 43813 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9138 ; free virtual = 43824 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 1c94b2d26 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.555 ; gain = 603.578 ; free physical = 9141 ; free virtual = 43827 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.555 ; gain = 667.609 ; free physical = 9141 ; free virtual = 43827 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9114 ; free virtual = 43801 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9113 ; free virtual = 43799 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9112 ; free virtual = 43798 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9109 ; free virtual = 43795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9108 ; free virtual = 43795 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9103 ; free virtual = 43789 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9103 ; free virtual = 43790 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9011 ; free virtual = 43697 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9010 ; free virtual = 43697 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8998 ; free virtual = 43685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8998 ; free virtual = 43685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8995 ; free virtual = 43681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8994 ; free virtual = 43680 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8988 ; free virtual = 43674 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8977 ; free virtual = 43663 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 8978 ; free virtual = 43664 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4ab841c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8846 ; free virtual = 43532 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8818 ; free virtual = 43504 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8730 ; free virtual = 43417 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 8688 ; free virtual = 43374 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8665 ; free virtual = 43351 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8662 ; free virtual = 43348 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 8656 ; free virtual = 43342 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 8656 ; free virtual = 43342 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8655 ; free virtual = 43342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8652 ; free virtual = 43338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8651 ; free virtual = 43337 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8649 ; free virtual = 43335 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8649 ; free virtual = 43335 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8639 ; free virtual = 43326 Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 8641 ; free virtual = 43327 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 8288 ; free virtual = 42975 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12020 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.953 ; gain = 0.000 ; free physical = 8214 ; free virtual = 42900 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1546.953 ; gain = 0.000 ; free physical = 8211 ; free virtual = 42898 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 1468.258 ; gain = 385.367 ; free physical = 8221 ; free virtual = 42907 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2053.934 ; gain = 120.668 ; free physical = 8208 ; free virtual = 42895 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 8179 ; free virtual = 42865 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 8179 ; free virtual = 42865 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8141 ; free virtual = 42828 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8107 ; free virtual = 42793 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8107 ; free virtual = 42793 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8107 ; free virtual = 42793 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8107 ; free virtual = 42794 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8107 ; free virtual = 42794 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8107 ; free virtual = 42794 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 8110 ; free virtual = 42797 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 8109 ; free virtual = 42796 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 8109 ; free virtual = 42796 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 8144 ; free virtual = 42830 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2106.766 ; gain = 205.516 ; free physical = 8143 ; free virtual = 42830 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2106.766 ; gain = 0.000 ; free physical = 8145 ; free virtual = 42833 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 8126 ; free virtual = 42813 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 8080 ; free virtual = 42766 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.168 ; gain = 43.668 ; free physical = 8093 ; free virtual = 42780 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.156 ; gain = 51.656 ; free physical = 8054 ; free virtual = 42741 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.156 ; gain = 51.656 ; free physical = 8054 ; free virtual = 42741 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 8029 ; free virtual = 42715 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 8001 ; free virtual = 42687 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7995 ; free virtual = 42681 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7995 ; free virtual = 42681 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7996 ; free virtual = 42683 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7996 ; free virtual = 42683 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7996 ; free virtual = 42683 Phase 7 Route finalize --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 7999 ; free virtual = 42686 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7996 ; free virtual = 42683 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.461 ; gain = 67.961 ; free physical = 7996 ; free virtual = 42683 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.461 ; gain = 67.961 ; free physical = 7971 ; free virtual = 42658 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.461 ; gain = 67.961 ; free physical = 8006 ; free virtual = 42692 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.250 ; gain = 138.766 ; free physical = 8004 ; free virtual = 42690 Writing placer database... Phase 1 Build RT Design | Checksum: 1610a2161 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2055.930 ; gain = 93.668 ; free physical = 7961 ; free virtual = 42648 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1610a2161 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.918 ; gain = 98.656 ; free physical = 7936 ; free virtual = 42623 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1610a2161 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.918 ; gain = 98.656 ; free physical = 7936 ; free virtual = 42623 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2129.250 ; gain = 0.000 ; free physical = 7967 ; free virtual = 42657 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.973 ; gain = 104.711 ; free physical = 7953 ; free virtual = 42640 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.934 ; gain = 93.668 ; free physical = 7941 ; free virtual = 42628 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 98.656 ; free physical = 7893 ; free virtual = 42580 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 98.656 ; free physical = 7887 ; free virtual = 42575 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7838 ; free virtual = 42525 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7821 ; free virtual = 42508 Phase 4 Rip-up And Reroute | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7820 ; free virtual = 42508 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7820 ; free virtual = 42507 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7819 ; free virtual = 42506 Phase 6 Post Hold Fix | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7820 ; free virtual = 42507 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 7811 ; free virtual = 42498 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.973 ; gain = 108.711 ; free physical = 7807 ; free virtual = 42495 Phase 9 Depositing Routes Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 927a5c4b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7805 ; free virtual = 42492 Phase 3 Initial Routing Phase 9 Depositing Routes | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.973 ; gain = 108.711 ; free physical = 7806 ; free virtual = 42493 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.973 ; gain = 108.711 ; free physical = 7837 ; free virtual = 42524 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2109.762 ; gain = 179.516 ; free physical = 7835 ; free virtual = 42522 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 7824 ; free virtual = 42512 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7818 ; free virtual = 42506 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7828 ; free virtual = 42516 Phase 4 Rip-up And Reroute | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7828 ; free virtual = 42516 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7829 ; free virtual = 42517 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7830 ; free virtual = 42517 Phase 6 Post Hold Fix | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 7831 ; free virtual = 42518 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] Running DRC as a precondition to command write_bitstream WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] Command: report_drc (run_mandatory_drcs) for: bitstream_checks WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] Congestion Report North Dir 1x1 Area, Max Cong = WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1123] No Congested Regions. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1464] Phase 7 Route finalize | Checksum: 927a5c4b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 7763 ; free virtual = 42450 Phase 8 Verifying routed nets WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1560] Verification completed successfully WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1584] Phase 8 Verifying routed nets | Checksum: 927a5c4b WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1608] Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 108.711 ; free physical = 7767 ; free virtual = 42454 Phase 9 Depositing Routes WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1872] Phase 9 Depositing Routes | Checksum: 927a5c4b WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1896] Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 108.711 ; free physical = 7768 ; free virtual = 42455 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2112] INFO: [Route 35-16] Router Completed Successfully WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2136] Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 108.711 ; free physical = 7799 ; free virtual = 42487 Routing Is Done. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2184] 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2110.766 ; gain = 179.516 ; free physical = 7797 ; free virtual = 42485 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 7783 ; free virtual = 42471 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 7395 ; free virtual = 42083 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 7397 ; free virtual = 42085 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 7387 ; free virtual = 42075 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 7387 ; free virtual = 42074 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 7387 ; free virtual = 42074 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 7386 ; free virtual = 42074 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 7386 ; free virtual = 42074 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 7385 ; free virtual = 42073 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2061.926 ; gain = 42.668 ; free physical = 6390 ; free virtual = 41078 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.914 ; gain = 48.656 ; free physical = 6318 ; free virtual = 41005 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.914 ; gain = 48.656 ; free physical = 6313 ; free virtual = 41001 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.969 ; gain = 58.711 ; free physical = 6186 ; free virtual = 40874 Phase 3 Initial Routing Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 6053 ; free virtual = 40740 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 6029 ; free virtual = 40717 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 6028 ; free virtual = 40716 Phase 5 Delay and Skew Optimization Loading route data... Processing options... Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 6025 ; free virtual = 40713 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 6017 ; free virtual = 40705 Creating bitmap... Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 6007 ; free virtual = 40695 Phase 7 Route finalize INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.441 ; gain = 0.000 ; free physical = 5985 ; free virtual = 40673 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 5962 ; free virtual = 40649 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 5955 ; free virtual = 40643 Phase 9 Depositing Routes Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 5934 ; free virtual = 40621 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 5968 ; free virtual = 40656 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2121.758 ; gain = 134.516 ; free physical = 5963 ; free virtual = 40651 Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.184 ; gain = 41.645 ; free physical = 5958 ; free virtual = 40646 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2075.172 ; gain = 47.633 ; free physical = 5919 ; free virtual = 40607 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2075.172 ; gain = 47.633 ; free physical = 5920 ; free virtual = 40607 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 5964 ; free virtual = 40654 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5903 ; free virtual = 40611 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 5876 ; free virtual = 40567 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5902 ; free virtual = 40592 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5916 ; free virtual = 40606 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5916 ; free virtual = 40606 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5916 ; free virtual = 40606 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5916 ; free virtual = 40606 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5916 ; free virtual = 40606 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Running DRC as a precondition to command write_bitstream WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5949 ; free virtual = 40639 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5948 ; free virtual = 40638 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5949 ; free virtual = 40639 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2097.227 ; gain = 69.688 ; free physical = 5985 ; free virtual = 40675 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.016 ; gain = 108.477 ; free physical = 5987 ; free virtual = 40677 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2136.016 ; gain = 0.000 ; free physical = 5932 ; free virtual = 40643 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2004.156 ; gain = 457.203 ; free physical = 5950 ; free virtual = 40660 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 5805 ; free virtual = 40495 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 5804 ; free virtual = 40494 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 5649 ; free virtual = 40343 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.156 ; gain = 457.203 ; free physical = 5418 ; free virtual = 40112 Phase 1.4 Constrain Clocks/Macros Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 5451 ; free virtual = 40145 Phase 1.3 Build Placer Netlist Model Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.156 ; gain = 457.203 ; free physical = 5452 ; free virtual = 40146 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2004.156 ; gain = 457.203 ; free physical = 5468 ; free virtual = 40162 Phase 2 Global Placement Creating bitstream... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Phase 1 Build RT Design | Checksum: d6a1f794 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.953 ; gain = 42.668 ; free physical = 5371 ; free virtual = 40065 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d6a1f794 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 5338 ; free virtual = 40032 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d6a1f794 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 5337 ; free virtual = 40031 Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.871 ; gain = 343.105 ; free physical = 5309 ; free virtual = 40003 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:23 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5356 ; free virtual = 40050 Phase 3 Initial Routing Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 6271 ; free virtual = 40966 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6247 ; free virtual = 40943 touch build/specimen_002/OK Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6247 ; free virtual = 40944 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 Phase 4 Rip-up And Reroute | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6246 ; free virtual = 40943 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6245 ; free virtual = 40943 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6241 ; free virtual = 40939 Phase 6 Post Hold Fix | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6239 ; free virtual = 40937 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b1023f3e Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 6349 ; free virtual = 41047 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b1023f3e Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 6355 ; free virtual = 41053 Phase 9 Depositing Routes Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 9 Depositing Routes | Checksum: 1b1023f3e Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.246 ; gain = 65.961 ; free physical = 6485 ; free virtual = 41184 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.246 ; gain = 65.961 ; free physical = 6518 ; free virtual = 41217 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2131.035 ; gain = 136.766 ; free physical = 6518 ; free virtual = 41217 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.555 ; gain = 0.000 ; free physical = 6767 ; free virtual = 41472 Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2131.035 ; gain = 0.000 ; free physical = 6767 ; free virtual = 41472 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.555 ; gain = 0.000 ; free physical = 6720 ; free virtual = 41425 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.555 ; gain = 0.000 ; free physical = 6720 ; free virtual = 41425 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 6770 ; free virtual = 41473 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 6722 ; free virtual = 41425 Phase 1.4 Constrain Clocks/Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 6701 ; free virtual = 41403 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 6676 ; free virtual = 41379 Number of Nodes with overlaps = 0 Writing bitstream ./design.bit... Phase 2 Router Initialization | Checksum: 12e953610 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6682 ; free virtual = 41385 Phase 3 Initial Routing Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 6694 ; free virtual = 41401 Phase 2 Global Placement Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 6764 ; free virtual = 41471 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6782 ; free virtual = 41489 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6798 ; free virtual = 41505 Phase 4 Rip-up And Reroute | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6798 ; free virtual = 41505 Phase 5 Delay and Skew Optimization Phase 3.3 Area Swap Optimization Phase 5 Delay and Skew Optimization | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6815 ; free virtual = 41522 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Running DRC as a precondition to command write_bitstream Phase 6.1 Hold Fix Iter | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6816 ; free virtual = 41523 Phase 6 Post Hold Fix | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6818 ; free virtual = 41525 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6857 ; free virtual = 41564 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6854 ; free virtual = 41561 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6962 ; free virtual = 41671 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 6998 ; free virtual = 41706 INFO: [Route 35-16] Router Completed Successfully Phase 3.4 Pipeline Register Optimization Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.238 ; gain = 8.684 ; free physical = 6997 ; free virtual = 41706 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2140.027 ; gain = 47.473 ; free physical = 6999 ; free virtual = 41708 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 7039 ; free virtual = 41746 Phase 3.5 Small Shape Detail Placement Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2140.027 ; gain = 0.000 ; free physical = 7031 ; free virtual = 41740 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 6939 ; free virtual = 41647 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2468.355 ; gain = 339.105 ; free physical = 6991 ; free virtual = 41698 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:28 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 7009 ; free virtual = 41717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.867 ; gain = 344.105 ; free physical = 7069 ; free virtual = 41777 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:28 2019... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 7987 ; free virtual = 42694 Phase 3.6 Re-assign LUT pins Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8889 ; free virtual = 43596 touch build/specimen_002/OK Phase 3.7 Pipeline Register Optimization GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8882 ; free virtual = 43590 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8741 ; free virtual = 43448 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 8726 ; free virtual = 43433 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8718 ; free virtual = 43425 Phase 4.2 Post Placement Cleanup --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8717 ; free virtual = 43425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 8710 ; free virtual = 43418 Phase 3.2 Commit Most Macros & LUTRAMs Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8697 ; free virtual = 43405 Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2452.871 ; gain = 342.105 ; free physical = 8801 ; free virtual = 43508 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:30 2019... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8809 ; free virtual = 43516 Phase 4.4 Final Placement Cleanup WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 8865 ; free virtual = 43572 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 8884 ; free virtual = 43592 Phase 3.3 Area Swap Optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 9729 ; free virtual = 44436 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9705 ; free virtual = 44412 Phase 3.4 Pipeline Register Optimization touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.203 ; gain = 553.250 ; free physical = 9707 ; free virtual = 44415 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.203 ; gain = 632.953 ; free physical = 9705 ; free virtual = 44413 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9723 ; free virtual = 44431 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9713 ; free virtual = 44421 --------------------------------------------------------------------------------- Loading data files... Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9688 ; free virtual = 44395 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9529 ; free virtual = 44237 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9534 ; free virtual = 44241 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9527 ; free virtual = 44234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9527 ; free virtual = 44234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9525 ; free virtual = 44233 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9522 ; free virtual = 44230 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9524 ; free virtual = 44231 INFO: [Project 1-571] Translating synthesized netlist Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Loading site data... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9396 ; free virtual = 44104 Phase 3.6 Re-assign LUT pins Loading data files... Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9368 ; free virtual = 44076 Phase 3.7 Pipeline Register Optimization Loading route data... Processing options... Creating bitmap... Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9360 ; free virtual = 44067 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9341 ; free virtual = 44049 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9315 ; free virtual = 44023 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9311 ; free virtual = 44019 Phase 4.3 Placer Reporting INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9293 ; free virtual = 44001 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9288 ; free virtual = 43995 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9276 ; free virtual = 43984 Creating bitstream... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9267 ; free virtual = 43975 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.211 ; gain = 630.953 ; free physical = 9267 ; free virtual = 43975 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2467.121 ; gain = 331.105 ; free physical = 9084 ; free virtual = 43799 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:42 2019... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. #of segments: 2 #of bits: 388 #of tags: 1 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.863 ; gain = 340.105 ; free physical = 10025 ; free virtual = 44740 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:46 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14226 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14306 Phase 1 Build RT Design | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2055.934 ; gain = 119.668 ; free physical = 10656 ; free virtual = 45373 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 10620 ; free virtual = 45337 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 109653c4d Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 10620 ; free virtual = 45337 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10597 ; free virtual = 45314 Phase 3 Initial Routing Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14346 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10589 ; free virtual = 45306 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10584 ; free virtual = 45301 Phase 4 Rip-up And Reroute | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10584 ; free virtual = 45301 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10584 ; free virtual = 45301 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10584 ; free virtual = 45300 Phase 6 Post Hold Fix | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10583 ; free virtual = 45300 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 130.711 ; free physical = 10585 ; free virtual = 45302 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 10584 ; free virtual = 45301 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 10583 ; free virtual = 45300 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 10617 ; free virtual = 45334 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2108.766 ; gain = 204.516 ; free physical = 10616 ; free virtual = 45333 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 10598 ; free virtual = 45317 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11075 ; free virtual = 45801 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 14428 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 10834 ; free virtual = 45560 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:14:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 10842 ; free virtual = 45568 --------------------------------------------------------------------------------- 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2470.141 ; gain = 339.105 ; free physical = 10847 ; free virtual = 45573 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:14:59 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 10949 ; free virtual = 45675 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 10952 ; free virtual = 45677 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 10950 ; free virtual = 45675 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:15:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2474.133 ; gain = 334.105 ; free physical = 11666 ; free virtual = 46393 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:15:00 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 Phase 1 Placer Initialization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 12558 ; free virtual = 47286 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.855 ; gain = 0.000 ; free physical = 12538 ; free virtual = 47266 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1558.855 ; gain = 0.000 ; free physical = 12554 ; free virtual = 47282 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 12518 ; free virtual = 47246 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12489 ; free virtual = 47217 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12475 ; free virtual = 47203 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12477 ; free virtual = 47205 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12475 ; free virtual = 47203 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] No constraint files found. WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12459 ; free virtual = 47188 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12471 ; free virtual = 47200 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12470 ; free virtual = 47199 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12446 ; free virtual = 47174 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 12270 ; free virtual = 46998 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12146 ; free virtual = 46874 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12141 ; free virtual = 46870 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12137 ; free virtual = 46866 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14614 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 12146 ; free virtual = 46875 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 12124 ; free virtual = 46853 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 12123 ; free virtual = 46852 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 12074 ; free virtual = 46804 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12070 ; free virtual = 46799 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12069 ; free virtual = 46798 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12066 ; free virtual = 46795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12063 ; free virtual = 46792 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12060 ; free virtual = 46790 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12059 ; free virtual = 46789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12058 ; free virtual = 46787 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12052 ; free virtual = 46781 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 12053 ; free virtual = 46782 INFO: [Project 1-571] Translating synthesized netlist Loading site data... WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14662 Creating bitstream... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11654 ; free virtual = 46383 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11645 ; free virtual = 46374 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11633 ; free virtual = 46362 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 11621 ; free virtual = 46350 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11609 ; free virtual = 46338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11605 ; free virtual = 46334 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11480 ; free virtual = 46213 --------------------------------------------------------------------------------- 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 11479 ; free virtual = 46212 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11474 ; free virtual = 46206 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11463 ; free virtual = 46196 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11461 ; free virtual = 46194 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11460 ; free virtual = 46193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11460 ; free virtual = 46193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11460 ; free virtual = 46193 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11456 ; free virtual = 46189 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 11456 ; free virtual = 46189 INFO: [Project 1-571] Translating synthesized netlist Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11652 ; free virtual = 46385 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11677 ; free virtual = 46410 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11746 ; free virtual = 46480 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11751 ; free virtual = 46485 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11757 ; free virtual = 46490 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11760 ; free virtual = 46493 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11759 ; free virtual = 46492 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 11772 ; free virtual = 46505 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 11775 ; free virtual = 46509 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 11792 ; free virtual = 46525 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 11792 ; free virtual = 46525 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 11589 ; free virtual = 46322 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 11572 ; free virtual = 46305 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11568 ; free virtual = 46301 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11564 ; free virtual = 46297 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11466 ; free virtual = 46199 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11465 ; free virtual = 46198 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11463 ; free virtual = 46196 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11460 ; free virtual = 46194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11459 ; free virtual = 46192 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11458 ; free virtual = 46191 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11457 ; free virtual = 46191 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 11455 ; free virtual = 46188 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11456 ; free virtual = 46189 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:15:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2450.871 ; gain = 342.105 ; free physical = 11336 ; free virtual = 46069 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:15:16 2019... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2129.961 ; gain = 29.758 ; free physical = 11369 ; free virtual = 46102 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.949 ; gain = 36.746 ; free physical = 11375 ; free virtual = 46108 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.949 ; gain = 36.746 ; free physical = 11376 ; free virtual = 46110 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 12244 ; free virtual = 46977 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 12210 ; free virtual = 46943 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12207 ; free virtual = 46941 --------------------------------------------------------------------------------- touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 30 #of tags: 3 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12181 ; free virtual = 46914 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12147 ; free virtual = 46880 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 12136 ; free virtual = 46869 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12077 ; free virtual = 46810 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 12078 ; free virtual = 46812 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12055 ; free virtual = 46788 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12055 ; free virtual = 46788 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12055 ; free virtual = 46788 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12055 ; free virtual = 46789 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12055 ; free virtual = 46789 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1405.918 ; gain = 323.031 ; free physical = 12077 ; free virtual = 46811 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12074 ; free virtual = 46807 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12071 ; free virtual = 46804 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12058 ; free virtual = 46792 INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.004 ; gain = 55.801 ; free physical = 12083 ; free virtual = 46816 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2194.793 ; gain = 94.590 ; free physical = 12080 ; free virtual = 46813 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 11965 ; free virtual = 46702 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 11887 ; free virtual = 46625 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.949 ; gain = 0.000 ; free physical = 11846 ; free virtual = 46586 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1470.949 ; gain = 0.000 ; free physical = 11832 ; free virtual = 46573 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2130.641 ; gain = 31.430 ; free physical = 11812 ; free virtual = 46553 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2135.629 ; gain = 36.418 ; free physical = 11770 ; free virtual = 46511 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2135.629 ; gain = 36.418 ; free physical = 11770 ; free virtual = 46511 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } Parameter DOA_REG bound to: 0 - type: integer ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ## proc putl {lst} { ## foreach line $lst {puts $line} ## } Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 # run Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11731 ; free virtual = 46476 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11737 ; free virtual = 46482 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11729 ; free virtual = 46476 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11729 ; free virtual = 46476 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11734 ; free virtual = 46481 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 3 Initial Routing | Checksum: 8a792087 No constraint files found. Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11744 ; free virtual = 46492 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 INFO: Launching helper process for spawning children vivado processes Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11797 ; free virtual = 46545 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11801 ; free virtual = 46549 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11801 ; free virtual = 46549 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11799 ; free virtual = 46547 Phase 6 Post Hold Fix | Checksum: 8a792087 INFO: Helper process launched with PID 14854 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11799 ; free virtual = 46547 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 11799 ; free virtual = 46547 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 7 Route finalize Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 11800 ; free virtual = 46548 Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11770 ; free virtual = 46519 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11769 ; free virtual = 46518 Phase 9 Depositing Routes Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11768 ; free virtual = 46517 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2156.684 ; gain = 57.473 ; free physical = 11802 ; free virtual = 46552 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:45 . Memory (MB): peak = 2195.473 ; gain = 96.262 ; free physical = 11802 ; free virtual = 46551 Writing placer database... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.793 ; gain = 0.000 ; free physical = 11637 ; free virtual = 46399 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14912 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.711 ; gain = 0.000 ; free physical = 11649 ; free virtual = 46413 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1462.711 ; gain = 0.000 ; free physical = 11649 ; free virtual = 46413 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 11519 ; free virtual = 46269 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2195.473 ; gain = 0.000 ; free physical = 11450 ; free virtual = 46208 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 11440 ; free virtual = 46199 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 11432 ; free virtual = 46191 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11437 ; free virtual = 46196 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11436 ; free virtual = 46172 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11435 ; free virtual = 46171 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11434 ; free virtual = 46170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11434 ; free virtual = 46170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11434 ; free virtual = 46170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11434 ; free virtual = 46170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11433 ; free virtual = 46170 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11433 ; free virtual = 46169 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 11433 ; free virtual = 46170 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 INFO: [Project 1-570] Preparing netlist for logic optimization Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 11246 ; free virtual = 45983 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 11211 ; free virtual = 45947 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 11193 ; free virtual = 45930 Phase 2 Final Placement Cleanup INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 11178 ; free virtual = 45919 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 11150 ; free virtual = 45886 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 11135 ; free virtual = 45871 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 11106 ; free virtual = 45843 --------------------------------------------------------------------------------- Loading data files... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 10995 ; free virtual = 45731 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10978 ; free virtual = 45715 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------ Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10835 ; free virtual = 45571 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10832 ; free virtual = 45568 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.434 ; gain = 55.992 ; free physical = 10835 ; free virtual = 45571 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10823 ; free virtual = 45560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10818 ; free virtual = 45555 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10818 ; free virtual = 45554 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10816 ; free virtual = 45552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10805 ; free virtual = 45542 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10785 ; free virtual = 45522 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 10772 ; free virtual = 45508 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 10426 ; free virtual = 45163 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10371 ; free virtual = 45108 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10363 ; free virtual = 45100 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10363 ; free virtual = 45100 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10363 ; free virtual = 45099 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10362 ; free virtual = 45099 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 10357 ; free virtual = 45094 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 10356 ; free virtual = 45093 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement Loading data files... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 10359 ; free virtual = 45095 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 10302 ; free virtual = 45039 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 10282 ; free virtual = 45020 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 10281 ; free virtual = 45018 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 10283 ; free virtual = 45020 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 10260 ; free virtual = 44998 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 10258 ; free virtual = 44995 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 10180 ; free virtual = 44917 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 10053 ; free virtual = 44790 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 10009 ; free virtual = 44746 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 10009 ; free virtual = 44746 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 10002 ; free virtual = 44740 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 9857 ; free virtual = 44594 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 9302 ; free virtual = 44039 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 9292 ; free virtual = 44029 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.438 ; gain = 0.000 ; free physical = 9255 ; free virtual = 43992 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.480 ; gain = 519.531 ; free physical = 9097 ; free virtual = 43835 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 9092 ; free virtual = 43830 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.480 ; gain = 519.531 ; free physical = 9083 ; free virtual = 43820 Phase 1.4 Constrain Clocks/Macros Loading site data... Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.480 ; gain = 519.531 ; free physical = 9032 ; free virtual = 43770 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.480 ; gain = 519.531 ; free physical = 9055 ; free virtual = 43792 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.480 ; gain = 519.531 ; free physical = 9045 ; free virtual = 43782 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.480 ; gain = 519.531 ; free physical = 9032 ; free virtual = 43770 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.480 ; gain = 584.562 ; free physical = 9031 ; free virtual = 43768 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 8991 ; free virtual = 43729 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 8976 ; free virtual = 43713 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 8955 ; free virtual = 43692 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 8942 ; free virtual = 43679 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 8939 ; free virtual = 43676 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 8943 ; free virtual = 43681 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 8943 ; free virtual = 43681 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15165 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 8421 ; free virtual = 43158 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.680 ; gain = 216.238 ; free physical = 8298 ; free virtual = 43036 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 8284 ; free virtual = 43021 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 8281 ; free virtual = 43018 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 8279 ; free virtual = 43016 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 8279 ; free virtual = 43016 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 8279 ; free virtual = 43016 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Loading site data... Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 469.531 ; free physical = 8279 ; free virtual = 43016 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 8279 ; free virtual = 43016 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.680 ; gain = 216.238 ; free physical = 8271 ; free virtual = 43008 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8262 ; free virtual = 43000 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8158 ; free virtual = 42896 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8157 ; free virtual = 42895 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8156 ; free virtual = 42893 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8155 ; free virtual = 42893 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8155 ; free virtual = 42892 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8155 ; free virtual = 42892 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8155 ; free virtual = 42892 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.664 ; gain = 225.223 ; free physical = 8155 ; free virtual = 42892 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8156 ; free virtual = 42893 INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 8129 ; free virtual = 42867 --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 8102 ; free virtual = 42839 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8098 ; free virtual = 42835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8400 ; free virtual = 43142 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8399 ; free virtual = 43141 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8399 ; free virtual = 43140 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8399 ; free virtual = 43140 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8398 ; free virtual = 43140 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8398 ; free virtual = 43139 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8398 ; free virtual = 43139 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8398 ; free virtual = 43140 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 8400 ; free virtual = 43141 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:15:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2532.898 ; gain = 338.105 ; free physical = 8454 ; free virtual = 43200 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:15:52 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 9428 ; free virtual = 44173 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.703 ; gain = 333.820 ; free physical = 9244 ; free virtual = 43990 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:923] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 8987 ; free virtual = 43733 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1539] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:16] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.734 ; gain = 0.000 ; free physical = 9028 ; free virtual = 43773 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1482.734 ; gain = 0.000 ; free physical = 9035 ; free virtual = 43785 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:15:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2534.578 ; gain = 339.105 ; free physical = 9044 ; free virtual = 43794 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:15:55 2019... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 9052 ; free virtual = 43797 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 9071 ; free virtual = 43817 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 9077 ; free virtual = 43823 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 9078 ; free virtual = 43824 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.949 ; gain = 115.508 ; free physical = 9679 ; free virtual = 44425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 10028 ; free virtual = 44774 Phase 1.3 Build Placer Netlist Model report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 10065 ; free virtual = 44811 Phase 1.4 Constrain Clocks/Macros Bitstream size: 4243411 bytes Starting Placer Task Config size: 1060815 words Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 10058 ; free virtual = 44804 Number of configuration frames: 9996 DONE INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 10062 ; free virtual = 44808 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 10058 ; free virtual = 44804 Phase 2 Final Placement Cleanup Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1296e3a58 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 10058 ; free virtual = 44803 Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 10054 ; free virtual = 44799 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 10052 ; free virtual = 44798 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 10051 ; free virtual = 44797 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 9499 ; free virtual = 44246 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 9482 ; free virtual = 44229 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 9478 ; free virtual = 44225 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 9477 ; free virtual = 44224 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 9476 ; free virtual = 44223 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 9476 ; free virtual = 44223 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 9476 ; free virtual = 44223 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 9476 ; free virtual = 44223 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 9320 ; free virtual = 44067 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 9333 ; free virtual = 44080 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9336 ; free virtual = 44083 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9259 ; free virtual = 44006 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9259 ; free virtual = 44006 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9258 ; free virtual = 44005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9258 ; free virtual = 44005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9258 ; free virtual = 44005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9258 ; free virtual = 44005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9257 ; free virtual = 44004 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 9258 ; free virtual = 44005 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9259 ; free virtual = 44006 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.930 ; gain = 342.047 ; free physical = 8945 ; free virtual = 43692 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 8894 ; free virtual = 43641 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e39310c0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 8894 ; free virtual = 43641 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.223 ; gain = 0.000 ; free physical = 8200 ; free virtual = 42947 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15573 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 511.531 ; free physical = 8154 ; free virtual = 42901 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 511.531 ; free physical = 8149 ; free virtual = 42896 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 511.531 ; free physical = 8146 ; free virtual = 42893 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 511.531 ; free physical = 8144 ; free virtual = 42891 Phase 2 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 8142 ; free virtual = 42889 Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 511.531 ; free physical = 8140 ; free virtual = 42887 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 511.531 ; free physical = 8139 ; free virtual = 42886 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.266 ; gain = 577.562 ; free physical = 8139 ; free virtual = 42886 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2134.070 ; gain = 49.668 ; free physical = 8121 ; free virtual = 42868 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e1594fd1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 8070 ; free virtual = 42817 Phase 1.3 Build Placer Netlist Model Phase 2.1 Fix Topology Constraints | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.059 ; gain = 58.656 ; free physical = 8068 ; free virtual = 42815 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2143.059 ; gain = 58.656 ; free physical = 8068 ; free virtual = 42815 Phase 1.3 Build Placer Netlist Model | Checksum: 278abb5b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 8066 ; free virtual = 42813 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 278abb5b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 8063 ; free virtual = 42810 Phase 1 Placer Initialization | Checksum: 278abb5b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 8064 ; free virtual = 42811 Phase 2 Global Placement ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 8031 ; free virtual = 42778 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 8039 ; free virtual = 42786 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 8032 ; free virtual = 42779 Phase 1 Build RT Design | Checksum: 9c37998b Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2054.934 ; gain = 121.668 ; free physical = 8030 ; free virtual = 42777 Phase 4 Rip-up And Reroute | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 8029 ; free virtual = 42776 Phase 5 Delay and Skew Optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 5 Delay and Skew Optimization | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 8022 ; free virtual = 42769 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 8004 ; free virtual = 42751 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9c37998b Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 7994 ; free virtual = 42742 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9c37998b Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 7994 ; free virtual = 42742 Phase 6 Post Hold Fix | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 7988 ; free virtual = 42735 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 7982 ; free virtual = 42729 Phase 8 Verifying routed nets Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 7973 ; free virtual = 42720 Phase 9 Depositing Routes INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7970 ; free virtual = 42718 Phase 3 Initial Routing WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 9 Depositing Routes | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 7958 ; free virtual = 42705 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.488 ; gain = 93.086 ; free physical = 7999 ; free virtual = 42746 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2216.277 ; gain = 163.891 ; free physical = 7999 ; free virtual = 42746 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7992 ; free virtual = 42740 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7990 ; free virtual = 42737 Phase 4 Rip-up And Reroute | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7990 ; free virtual = 42737 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7990 ; free virtual = 42737 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7990 ; free virtual = 42737 Phase 6 Post Hold Fix | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7990 ; free virtual = 42737 INFO: Launching helper process for spawning children vivado processes Phase 7 Route finalize INFO: Helper process launched with PID 16256 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2064.977 ; gain = 131.711 ; free physical = 7997 ; free virtual = 42744 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 7996 ; free virtual = 42743 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 7995 ; free virtual = 42742 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 8029 ; free virtual = 42776 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2106.766 ; gain = 205.516 ; free physical = 8029 ; free virtual = 42776 Writing placer database... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2106.766 ; gain = 0.000 ; free physical = 8027 ; free virtual = 42777 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7969 ; free virtual = 42722 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7957 ; free virtual = 42710 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 215570181 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7938 ; free virtual = 42692 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ef31df4c Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7925 ; free virtual = 42679 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b8e63fb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7921 ; free virtual = 42676 Phase 3.5 Small Shape Detail Placement Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7980 ; free virtual = 42738 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7980 ; free virtual = 42737 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7978 ; free virtual = 42736 Phase 3 Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7976 ; free virtual = 42734 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7973 ; free virtual = 42731 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7967 ; free virtual = 42726 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7968 ; free virtual = 42727 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7965 ; free virtual = 42725 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7966 ; free virtual = 42725 Ending Placer Task | Checksum: 146bf3d33 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 7978 ; free virtual = 42737 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 659.605 ; free physical = 7978 ; free virtual = 42737 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2216.277 ; gain = 0.000 ; free physical = 7865 ; free virtual = 42640 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 621f9429 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2216.277 ; gain = 0.000 ; free physical = 7881 ; free virtual = 42631 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.164 ; gain = 45.668 ; free physical = 7794 ; free virtual = 42544 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.152 ; gain = 51.656 ; free physical = 7754 ; free virtual = 42504 Phase 2.2 Pre Route Cleanup --------------------------------------------------------------------------------- Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.152 ; gain = 51.656 ; free physical = 7752 ; free virtual = 42502 Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 7752 ; free virtual = 42502 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.457 ; gain = 61.961 ; free physical = 7755 ; free virtual = 42505 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.172 ; gain = 43.668 ; free physical = 7754 ; free virtual = 42504 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 7714 ; free virtual = 42464 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 7713 ; free virtual = 42464 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7614 ; free virtual = 42365 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7594 ; free virtual = 42345 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7588 ; free virtual = 42339 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7585 ; free virtual = 42336 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7577 ; free virtual = 42327 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7574 ; free virtual = 42325 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Number of Nodes with overlaps = 0 Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.457 ; gain = 63.961 ; free physical = 7572 ; free virtual = 42323 Phase 8 Verifying routed nets Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2083.465 ; gain = 60.961 ; free physical = 7570 ; free virtual = 42320 Phase 3 Initial Routing Loading data files... Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.457 ; gain = 66.961 ; free physical = 7571 ; free virtual = 42321 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.457 ; gain = 66.961 ; free physical = 7558 ; free virtual = 42309 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.457 ; gain = 66.961 ; free physical = 7591 ; free virtual = 42342 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.246 ; gain = 137.766 ; free physical = 7590 ; free virtual = 42341 Number of Nodes with overlaps = 0 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Phase 3 Initial Routing | Checksum: 5700a6dd Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7584 ; free virtual = 42335 Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Writing placer database... INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:475] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7589 ; free virtual = 42339 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7588 ; free virtual = 42339 Phase 5 Delay and Skew Optimization INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:615] Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:643] Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7588 ; free virtual = 42338 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:671] Phase 6 Post Hold Fix WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:699] Phase 6.1 Hold Fix Iter WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1371] Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7582 ; free virtual = 42333 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1791] Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7582 ; free virtual = 42333 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 7 Route finalize WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:16] Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Writing XDEF routing. Phase 1 Build RT Design | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2056.926 ; gain = 92.668 ; free physical = 7550 ; free virtual = 42302 Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 7552 ; free virtual = 42304 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 7560 ; free virtual = 42313 Phase 9 Depositing Routes Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1016daa37 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 7538 ; free virtual = 42292 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1016daa37 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 7536 ; free virtual = 42289 Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.78 . Memory (MB): peak = 2128.246 ; gain = 0.000 ; free physical = 7536 ; free virtual = 42289 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 7545 ; free virtual = 42300 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.465 ; gain = 66.961 ; free physical = 7583 ; free virtual = 42339 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.254 ; gain = 137.766 ; free physical = 7582 ; free virtual = 42339 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 7607 ; free virtual = 42362 --------------------------------------------------------------------------------- Writing placer database... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7619 ; free virtual = 42371 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 7584 ; free virtual = 42337 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 7583 ; free virtual = 42336 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 7564 ; free virtual = 42319 INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7505 ; free virtual = 42261 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7491 ; free virtual = 42242 Phase 4 Rip-up And Reroute | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7490 ; free virtual = 42242 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7490 ; free virtual = 42242 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7489 ; free virtual = 42241 Phase 6 Post Hold Fix | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7489 ; free virtual = 42241 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 7477 ; free virtual = 42229 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 7473 ; free virtual = 42225 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: aef8114b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 7469 ; free virtual = 42221 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 7498 ; free virtual = 42250 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.758 ; gain = 178.516 ; free physical = 7495 ; free virtual = 42247 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 7494 ; free virtual = 42246 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2110.758 ; gain = 0.000 ; free physical = 7451 ; free virtual = 42204 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 7333 ; free virtual = 42086 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.449 ; gain = 0.000 ; free physical = 6520 ; free virtual = 41273 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 190af02d6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6425 ; free virtual = 41178 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6423 ; free virtual = 41175 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6413 ; free virtual = 41166 Phase 1 Placer Initialization | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6408 ; free virtual = 41160 Phase 2 Global Placement WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:16] Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 6178 ; free virtual = 40931 --------------------------------------------------------------------------------- Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 6170 ; free virtual = 40924 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 6124 ; free virtual = 40883 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 6102 ; free virtual = 40861 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 6105 ; free virtual = 40859 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 6103 ; free virtual = 40856 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5978 ; free virtual = 40731 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5975 ; free virtual = 40728 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5972 ; free virtual = 40725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5972 ; free virtual = 40725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5971 ; free virtual = 40724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5970 ; free virtual = 40723 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5969 ; free virtual = 40723 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.496 ; free physical = 5964 ; free virtual = 40717 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.949 ; gain = 246.496 ; free physical = 5965 ; free virtual = 40718 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... Phase 2 Global Placement | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5871 ; free virtual = 40624 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5862 ; free virtual = 40615 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b3a364ee Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5861 ; free virtual = 40614 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d7e42b9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5851 ; free virtual = 40604 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 15732a31e Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5851 ; free virtual = 40604 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5816 ; free virtual = 40569 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5810 ; free virtual = 40563 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5809 ; free virtual = 40562 Phase 3 Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5808 ; free virtual = 40561 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5807 ; free virtual = 40560 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5798 ; free virtual = 40551 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5798 ; free virtual = 40551 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5798 ; free virtual = 40551 INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5798 ; free virtual = 40551 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Ending Placer Task | Checksum: 181b67064 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.539 ; gain = 603.578 ; free physical = 5817 ; free virtual = 40570 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.539 ; gain = 667.609 ; free physical = 5817 ; free virtual = 40570 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 5751 ; free virtual = 40504 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.086 ; gain = 171.469 ; free physical = 5726 ; free virtual = 40479 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 5701 ; free virtual = 40454 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 5702 ; free virtual = 40455 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 5639 ; free virtual = 40394 Phase 3 Initial Routing WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9d16c75a ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5846 ; free virtual = 40603 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5877 ; free virtual = 40634 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5880 ; free virtual = 40637 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5883 ; free virtual = 40640 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Vivado 12-1842] Bitgen Completed Successfully. Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5886 ; free virtual = 40643 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5885 ; free virtual = 40642 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 5880 ; free virtual = 40637 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 5871 ; free virtual = 40628 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 5871 ; free virtual = 40628 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 5908 ; free virtual = 40666 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 5907 ; free virtual = 40664 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 5857 ; free virtual = 40617 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.941 ; gain = 342.055 ; free physical = 5653 ; free virtual = 40411 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:16:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2063.926 ; gain = 44.668 ; free physical = 5547 ; free virtual = 40305 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2450.871 ; gain = 344.105 ; free physical = 5546 ; free virtual = 40304 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:16:47 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 5510 ; free virtual = 40267 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 5509 ; free virtual = 40266 Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 6409 ; free virtual = 41167 Phase 3 Initial Routing Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 6393 ; free virtual = 41150 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a69706bf Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 6389 ; free virtual = 41147 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6383 ; free virtual = 41141 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Loading route data... Processing options... Creating bitmap... Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6361 ; free virtual = 41119 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6360 ; free virtual = 41118 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6359 ; free virtual = 41117 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6356 ; free virtual = 41114 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6354 ; free virtual = 41112 Phase 7 Route finalize No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 6289 ; free virtual = 41047 Phase 8 Verifying routed nets Verification completed successfully Loading route data... Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 6282 ; free virtual = 41040 Phase 9 Depositing Routes Processing options... Creating bitmap... Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 6241 ; free virtual = 40998 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 6274 ; free virtual = 41032 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2121.758 ; gain = 134.516 ; free physical = 6273 ; free virtual = 41031 Writing placer database... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.680 ; gain = 249.062 ; free physical = 6276 ; free virtual = 41034 --------------------------------------------------------------------------------- Writing XDEF routing. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 6268 ; free virtual = 41028 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.680 ; gain = 249.062 ; free physical = 6267 ; free virtual = 41027 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6214 ; free virtual = 40972 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6163 ; free virtual = 40921 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6153 ; free virtual = 40911 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6125 ; free virtual = 40883 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6122 ; free virtual = 40880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6120 ; free virtual = 40879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6121 ; free virtual = 40880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6120 ; free virtual = 40878 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.703 ; gain = 270.086 ; free physical = 6117 ; free virtual = 40876 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.711 ; gain = 270.086 ; free physical = 6122 ; free virtual = 40881 INFO: [Project 1-571] Translating synthesized netlist Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2472.359 ; gain = 344.105 ; free physical = 6517 ; free virtual = 41287 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:00 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Creating bitstream... 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2471.352 ; gain = 343.105 ; free physical = 7398 ; free virtual = 42170 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:02 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:04 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading site data... 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 2452.863 ; gain = 342.105 ; free physical = 8237 ; free virtual = 43009 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:04 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1467.375 ; gain = 384.484 ; free physical = 9198 ; free virtual = 43970 Writing bitstream ./design.bit... Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1551.078 ; gain = 0.000 ; free physical = 9544 ; free virtual = 44320 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1551.078 ; gain = 0.000 ; free physical = 9537 ; free virtual = 44313 Creating bitstream... Loading site data... Phase 1 Build RT Design | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.949 ; gain = 42.668 ; free physical = 9372 ; free virtual = 44148 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2075.938 ; gain = 49.656 ; free physical = 9332 ; free virtual = 44108 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2075.938 ; gain = 49.656 ; free physical = 9331 ; free virtual = 44107 Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2088.242 ; gain = 61.961 ; free physical = 9110 ; free virtual = 43886 Phase 3 Initial Routing INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:44 . Memory (MB): peak = 2604.938 ; gain = 388.660 ; free physical = 9075 ; free virtual = 43852 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:09 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9106 ; free virtual = 43880 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9122 ; free virtual = 43896 Phase 4 Rip-up And Reroute | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9122 ; free virtual = 43897 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9125 ; free virtual = 43900 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 6.1 Hold Fix Iter | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9128 ; free virtual = 43902 Phase 6 Post Hold Fix | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9128 ; free virtual = 43903 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 9143 ; free virtual = 43917 Phase 7 Route finalize Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2090.242 ; gain = 63.961 ; free physical = 9670 ; free virtual = 44445 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2093.242 ; gain = 66.961 ; free physical = 9746 ; free virtual = 44521 Phase 9 Depositing Routes Bitstream size: 4243411 bytes Phase 9 Depositing Routes | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2093.242 ; gain = 66.961 ; free physical = 10158 ; free virtual = 44933 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2093.242 ; gain = 66.961 ; free physical = 10195 ; free virtual = 44969 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2132.031 ; gain = 137.766 ; free physical = 10195 ; free virtual = 44969 Config size: 1060815 words Number of configuration frames: 9996 DONE Writing placer database... Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2132.031 ; gain = 0.000 ; free physical = 10176 ; free virtual = 44959 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1 Build RT Design | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 10219 ; free virtual = 45003 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 151febe35 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 10231 ; free virtual = 45015 Phase 1.3 Build Placer Netlist Model Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 10216 ; free virtual = 45000 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 10218 ; free virtual = 45002 Phase 1.3 Build Placer Netlist Model | Checksum: 1e951241b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 10216 ; free virtual = 45000 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e951241b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 10229 ; free virtual = 45013 touch build/specimen_002/OK Phase 1 Placer Initialization | Checksum: 1e951241b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 10231 ; free virtual = 45015 Phase 2 Global Placement GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17f6b07bf Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10325 ; free virtual = 45106 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10340 ; free virtual = 45126 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10329 ; free virtual = 45115 Phase 4 Rip-up And Reroute | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10328 ; free virtual = 45114 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10338 ; free virtual = 45124 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10338 ; free virtual = 45124 Phase 6 Post Hold Fix | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10338 ; free virtual = 45124 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10384 ; free virtual = 45170 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10383 ; free virtual = 45169 Phase 9 Depositing Routes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18072 Phase 9 Depositing Routes | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10388 ; free virtual = 45174 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 10424 ; free virtual = 45210 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2140.023 ; gain = 55.477 ; free physical = 10424 ; free virtual = 45209 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2140.023 ; gain = 0.000 ; free physical = 10383 ; free virtual = 45172 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2472.363 ; gain = 344.105 ; free physical = 10313 ; free virtual = 45100 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:14 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 2 Global Placement | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11246 ; free virtual = 46033 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 3.1 Commit Multi Column Macros | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11254 ; free virtual = 46041 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 262698c70 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11251 ; free virtual = 46037 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23c446a3b Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11212 ; free virtual = 45998 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 205f8caa0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11207 ; free virtual = 45993 Phase 3.5 Small Shape Detail Placement Creating bitstream... Phase 3.5 Small Shape Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11114 ; free virtual = 45901 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11088 ; free virtual = 45875 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11085 ; free virtual = 45871 Phase 3 Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11077 ; free virtual = 45864 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11061 ; free virtual = 45848 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11048 ; free virtual = 45835 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11043 ; free virtual = 45829 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11040 ; free virtual = 45826 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11037 ; free virtual = 45824 Ending Placer Task | Checksum: 1a3769583 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 11054 ; free virtual = 45841 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.551 ; gain = 667.609 ; free physical = 11054 ; free virtual = 45841 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: bed6ec79 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10877 ; free virtual = 45673 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:33 . Memory (MB): peak = 2460.863 ; gain = 339.105 ; free physical = 10863 ; free virtual = 45659 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:22 2019... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18549 touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11660 ; free virtual = 46458 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 11605 ; free virtual = 46403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 11605 ; free virtual = 46402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 11607 ; free virtual = 46404 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18622 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18704 Phase 1 Build RT Design | Checksum: 137afd744 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 10890 ; free virtual = 45687 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137afd744 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 10856 ; free virtual = 45653 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137afd744 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.539 ; gain = 0.000 ; free physical = 10855 ; free virtual = 45652 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.566 ; gain = 0.000 ; free physical = 10846 ; free virtual = 45643 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11278bc6b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10648 ; free virtual = 45445 Phase 3 Initial Routing Loading site data... Loading route data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10638 ; free virtual = 45436 Processing options... Creating bitmap... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10630 ; free virtual = 45428 Phase 4 Rip-up And Reroute | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10630 ; free virtual = 45428 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10630 ; free virtual = 45428 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10630 ; free virtual = 45428 Phase 6 Post Hold Fix | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10612 ; free virtual = 45410 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10561 ; free virtual = 45358 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10552 ; free virtual = 45349 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10530 ; free virtual = 45327 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.223 ; gain = 9.684 ; free physical = 10567 ; free virtual = 45364 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2141.012 ; gain = 48.473 ; free physical = 10567 ; free virtual = 45364 Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.281 ; gain = 452.203 ; free physical = 10635 ; free virtual = 45433 Phase 1.3 Build Placer Netlist Model Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2141.012 ; gain = 0.000 ; free physical = 10634 ; free virtual = 45434 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.281 ; gain = 452.203 ; free physical = 10451 ; free virtual = 45249 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10424 ; free virtual = 45222 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.281 ; gain = 452.203 ; free physical = 10425 ; free virtual = 45223 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 10422 ; free virtual = 45220 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 10384 ; free virtual = 45181 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10366 ; free virtual = 45163 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.281 ; gain = 452.203 ; free physical = 10374 ; free virtual = 45172 Phase 2 Global Placement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10418 ; free virtual = 45215 --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10315 ; free virtual = 45113 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10312 ; free virtual = 45110 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10311 ; free virtual = 45108 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10310 ; free virtual = 45107 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10308 ; free virtual = 45106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10307 ; free virtual = 45105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | INFO: Helper process launched with PID 19125 +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10305 ; free virtual = 45103 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10303 ; free virtual = 45101 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10304 ; free virtual = 45102 Creating bitstream... INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10219 ; free virtual = 45017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10206 ; free virtual = 45004 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10205 ; free virtual = 45003 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10170 ; free virtual = 44968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10028 ; free virtual = 44830 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Writing bitstream ./design.bit... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10122 ; free virtual = 44925 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10199 ; free virtual = 45005 --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10387 ; free virtual = 45193 Phase 3.3 Area Swap Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10480 ; free virtual = 45287 Phase 3.4 Pipeline Register Optimization WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:16] Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10489 ; free virtual = 45295 INFO: Launching helper process for spawning children vivado processes Phase 3.5 Small Shape Detail Placement INFO: Helper process launched with PID 19474 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1401.684 ; gain = 318.797 ; free physical = 10431 ; free virtual = 45238 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10489 ; free virtual = 45302 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 10491 ; free virtual = 45305 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1465.715 ; gain = 0.000 ; free physical = 10491 ; free virtual = 45305 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10497 ; free virtual = 45304 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10499 ; free virtual = 45307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10502 ; free virtual = 45309 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10514 ; free virtual = 45322 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10476 ; free virtual = 45289 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10456 ; free virtual = 45263 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 10456 ; free virtual = 45263 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10446 ; free virtual = 45253 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10414 ; free virtual = 45221 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10369 ; free virtual = 45176 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10341 ; free virtual = 45148 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10305 ; free virtual = 45112 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10289 ; free virtual = 45096 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10269 ; free virtual = 45076 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 2469.137 ; gain = 337.105 ; free physical = 10273 ; free virtual = 45080 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:43 2019... Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10268 ; free virtual = 45075 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:17:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2474.129 ; gain = 334.105 ; free physical = 10352 ; free virtual = 45158 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:17:44 2019... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.324 ; gain = 540.246 ; free physical = 10412 ; free virtual = 45219 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.324 ; gain = 623.949 ; free physical = 10419 ; free virtual = 45225 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 12077 ; free virtual = 46886 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 11973 ; free virtual = 46782 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 11951 ; free virtual = 46761 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Routing Task Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11951 ; free virtual = 46760 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 11924 ; free virtual = 46735 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11869 ; free virtual = 46680 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11855 ; free virtual = 46666 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11851 ; free virtual = 46661 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11850 ; free virtual = 46661 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11872 ; free virtual = 46682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11872 ; free virtual = 46682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11871 ; free virtual = 46681 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 11868 ; free virtual = 46678 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 11867 ; free virtual = 46677 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19758 Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11622 ; free virtual = 46432 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 11620 ; free virtual = 46431 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11618 ; free virtual = 46429 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11617 ; free virtual = 46427 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 11560 ; free virtual = 46370 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 11534 ; free virtual = 46344 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11504 ; free virtual = 46314 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11502 ; free virtual = 46312 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11499 ; free virtual = 46310 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11499 ; free virtual = 46309 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11497 ; free virtual = 46307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11496 ; free virtual = 46307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11492 ; free virtual = 46302 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11493 ; free virtual = 46304 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 11494 ; free virtual = 46305 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11460 ; free virtual = 46271 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 11455 ; free virtual = 46266 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1992] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11441 ; free virtual = 46252 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11440 ; free virtual = 46250 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11430 ; free virtual = 46240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11428 ; free virtual = 46239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11427 ; free virtual = 46238 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11425 ; free virtual = 46236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11424 ; free virtual = 46235 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 11422 ; free virtual = 46232 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 11422 ; free virtual = 46233 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 11399 ; free virtual = 46210 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 11396 ; free virtual = 46207 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 11186 ; free virtual = 45996 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 11422 ; free virtual = 46237 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 11383 ; free virtual = 46197 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 11381 ; free virtual = 46196 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 11224 ; free virtual = 46040 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 11206 ; free virtual = 46021 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 11165 ; free virtual = 45985 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 11165 ; free virtual = 45984 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 11159 ; free virtual = 45974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 11161 ; free virtual = 45977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 11156 ; free virtual = 45971 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: eb842b41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10993 ; free virtual = 45809 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10939 ; free virtual = 45754 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10930 ; free virtual = 45745 Phase 4 Rip-up And Reroute | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10929 ; free virtual = 45744 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10928 ; free virtual = 45743 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10927 ; free virtual = 45742 Phase 6 Post Hold Fix | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10926 ; free virtual = 45741 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10872 ; free virtual = 45687 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10867 ; free virtual = 45682 Phase 9 Depositing Routes INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] Phase 9 Depositing Routes | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10834 ; free virtual = 45649 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 10865 ; free virtual = 45680 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2141.023 ; gain = 48.473 ; free physical = 10862 ; free virtual = 45677 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:18:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2141.023 ; gain = 0.000 ; free physical = 10830 ; free virtual = 45648 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2474.117 ; gain = 333.105 ; free physical = 10829 ; free virtual = 45647 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:18:02 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.203 ; gain = 0.000 ; free physical = 10919 ; free virtual = 45746 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 11746 ; free virtual = 46579 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 11743 ; free virtual = 46576 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 11742 ; free virtual = 46576 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 11742 ; free virtual = 46576 Phase 2 Final Placement Cleanup DONE Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 11747 ; free virtual = 46580 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 435.531 ; free physical = 11745 ; free virtual = 46579 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.246 ; gain = 499.562 ; free physical = 11745 ; free virtual = 46579 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11768 ; free virtual = 46587 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 11755 ; free virtual = 46593 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11711 ; free virtual = 46529 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11709 ; free virtual = 46527 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 11524 ; free virtual = 46342 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 11560 ; free virtual = 46379 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11484 ; free virtual = 46304 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 20001 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 11482 ; free virtual = 46314 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 11445 ; free virtual = 46284 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11438 ; free virtual = 46277 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20041 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11326 ; free virtual = 46146 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11323 ; free virtual = 46143 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11315 ; free virtual = 46135 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11313 ; free virtual = 46133 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11310 ; free virtual = 46130 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11310 ; free virtual = 46130 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11308 ; free virtual = 46128 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11307 ; free virtual = 46127 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11306 ; free virtual = 46126 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 11301 ; free virtual = 46121 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 11300 ; free virtual = 46120 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 1336.070 ; gain = 240.152 ; free physical = 11123 ; free virtual = 45954 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 10567 ; free virtual = 45432 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 10484 ; free virtual = 45348 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 10453 ; free virtual = 45317 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 1347.070 ; gain = 251.152 ; free physical = 10442 ; free virtual = 45307 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 10377 ; free virtual = 45241 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 10391 ; free virtual = 45255 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 10385 ; free virtual = 45250 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 10383 ; free virtual = 45248 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 10369 ; free virtual = 45233 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 10369 ; free virtual = 45234 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 10369 ; free virtual = 45233 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 10355 ; free virtual = 45219 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10349 ; free virtual = 45213 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 10215 ; free virtual = 45079 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 10219 ; free virtual = 45083 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 10199 ; free virtual = 45063 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10171 ; free virtual = 45035 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10161 ; free virtual = 45025 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10049 ; free virtual = 44913 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10014 ; free virtual = 44878 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9982 ; free virtual = 44847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9961 ; free virtual = 44825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9955 ; free virtual = 44819 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 9942 ; free virtual = 44807 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1352.086 ; gain = 256.160 ; free physical = 9934 ; free virtual = 44798 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1355.102 ; gain = 259.184 ; free physical = 9879 ; free virtual = 44743 --------------------------------------------------------------------------------- Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 9791 ; free virtual = 44655 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1355.102 ; gain = 259.184 ; free physical = 9798 ; free virtual = 44663 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 9774 ; free virtual = 44638 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9738 ; free virtual = 44602 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9735 ; free virtual = 44599 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9735 ; free virtual = 44599 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9735 ; free virtual = 44599 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9735 ; free virtual = 44599 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9736 ; free virtual = 44600 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 9735 ; free virtual = 44599 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9745 ; free virtual = 44610 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9754 ; free virtual = 44623 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9745 ; free virtual = 44610 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9745 ; free virtual = 44610 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9719 ; free virtual = 44584 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9627 ; free virtual = 44492 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9617 ; free virtual = 44482 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9597 ; free virtual = 44461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9553 ; free virtual = 44418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9576 ; free virtual = 44441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9571 ; free virtual = 44436 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9570 ; free virtual = 44435 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 9568 ; free virtual = 44433 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.086 ; gain = 267.160 ; free physical = 9570 ; free virtual = 44434 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:16] Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 9140 ; free virtual = 44009 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 9118 ; free virtual = 43984 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 9043 ; free virtual = 43909 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 9032 ; free virtual = 43898 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 9188 ; free virtual = 44058 Phase 1.3 Build Placer Netlist Model INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20260 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 8985 ; free virtual = 43855 --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 8987 ; free virtual = 43857 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 8978 ; free virtual = 43848 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8974 ; free virtual = 43844 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8936 ; free virtual = 43806 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8935 ; free virtual = 43805 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8934 ; free virtual = 43804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8934 ; free virtual = 43804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8935 ; free virtual = 43805 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8933 ; free virtual = 43802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8933 ; free virtual = 43802 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8932 ; free virtual = 43801 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8933 ; free virtual = 43802 INFO: [Project 1-571] Translating synthesized netlist Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2129.086 ; gain = 37.762 ; free physical = 8903 ; free virtual = 43773 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.074 ; gain = 44.750 ; free physical = 8869 ; free virtual = 43738 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.074 ; gain = 44.750 ; free physical = 8869 ; free virtual = 43738 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:18:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.129 ; gain = 334.105 ; free physical = 8871 ; free virtual = 43740 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:18:33 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 8875 ; free virtual = 43745 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 9394 ; free virtual = 44263 Bitstream size: 4243411 bytes Config size: 1060815 words Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9845 ; free virtual = 44714 Number of configuration frames: 9996 Phase 3 Initial Routing DONE Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 9851 ; free virtual = 44721 Phase 2 Global Placement touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9796 ; free virtual = 44665 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9793 ; free virtual = 44663 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9793 ; free virtual = 44663 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9793 ; free virtual = 44663 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9793 ; free virtual = 44663 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9793 ; free virtual = 44663 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9750 ; free virtual = 44620 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9747 ; free virtual = 44617 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9738 ; free virtual = 44608 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.129 ; gain = 63.805 ; free physical = 9769 ; free virtual = 44639 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:50 . Memory (MB): peak = 2193.918 ; gain = 102.594 ; free physical = 9765 ; free virtual = 44635 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing placer database... INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1343.559 ; gain = 247.938 ; free physical = 9642 ; free virtual = 44529 --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9591 ; free virtual = 44479 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1343.559 ; gain = 247.938 ; free physical = 9604 ; free virtual = 44492 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9569 ; free virtual = 44459 Phase 3.2 Commit Most Macros & LUTRAMs Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.918 ; gain = 0.000 ; free physical = 9530 ; free virtual = 44423 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9527 ; free virtual = 44420 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9469 ; free virtual = 44363 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9401 ; free virtual = 44295 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9349 ; free virtual = 44221 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9328 ; free virtual = 44200 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9294 ; free virtual = 44166 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9293 ; free virtual = 44165 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 9291 ; free virtual = 44163 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9319 ; free virtual = 44191 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9329 ; free virtual = 44200 --------------------------------------------------------------------------------- 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 9346 ; free virtual = 44217 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9348 ; free virtual = 44220 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9358 ; free virtual = 44230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9363 ; free virtual = 44235 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9362 ; free virtual = 44234 INFO: [DRC 23-27] Running DRC with 8 threads Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.590 ; gain = 268.961 ; free physical = 9363 ; free virtual = 44235 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9343 ; free virtual = 44215 Phase 1.3 Build Placer Netlist Model Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9343 ; free virtual = 44215 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9342 ; free virtual = 44214 Running DRC as a precondition to command write_bitstream Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9342 ; free virtual = 44214 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9340 ; free virtual = 44212 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9331 ; free virtual = 44203 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 9331 ; free virtual = 44203 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 9253 ; free virtual = 44124 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 9251 ; free virtual = 44123 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9261 ; free virtual = 44133 Phase 3.6 Re-assign LUT pins INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9305 ; free virtual = 44178 Phase 3.7 Pipeline Register Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9304 ; free virtual = 44176 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9306 ; free virtual = 44178 Starting Routing Task INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9314 ; free virtual = 44186 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9314 ; free virtual = 44187 --------------------------------------------------------------------------------- Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9308 ; free virtual = 44180 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9296 ; free virtual = 44168 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9314 ; free virtual = 44186 Phase 4.2 Post Placement Cleanup 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 9331 ; free virtual = 44203 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9305 ; free virtual = 44177 Phase 4.3 Placer Reporting INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9275 ; free virtual = 44147 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9221 ; free virtual = 44093 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9155 ; free virtual = 44027 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9179 ; free virtual = 44051 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 630.953 ; free physical = 9183 ; free virtual = 44055 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1541.867 ; gain = 0.000 ; free physical = 9099 ; free virtual = 43971 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1541.867 ; gain = 0.000 ; free physical = 9069 ; free virtual = 43941 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 8949 ; free virtual = 43821 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2054.930 ; gain = 121.668 ; free physical = 8780 ; free virtual = 43652 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2059.918 ; gain = 126.656 ; free physical = 8705 ; free virtual = 43577 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2059.918 ; gain = 126.656 ; free physical = 8704 ; free virtual = 43576 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8702 ; free virtual = 43574 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8563 ; free virtual = 43435 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8542 ; free virtual = 43414 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8542 ; free virtual = 43414 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8542 ; free virtual = 43414 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8542 ; free virtual = 43414 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8541 ; free virtual = 43413 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.973 ; gain = 132.711 ; free physical = 8535 ; free virtual = 43407 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 135.711 ; free physical = 8536 ; free virtual = 43408 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 135.711 ; free physical = 8535 ; free virtual = 43407 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 135.711 ; free physical = 8569 ; free virtual = 43441 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2107.762 ; gain = 206.516 ; free physical = 8568 ; free virtual = 43440 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2107.762 ; gain = 0.000 ; free physical = 8637 ; free virtual = 43511 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 8583 ; free virtual = 43455 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.67 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 8535 ; free virtual = 43407 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 8578 ; free virtual = 43451 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 8566 ; free virtual = 43439 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8579 ; free virtual = 43451 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 8599 ; free virtual = 43472 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8545 ; free virtual = 43418 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8537 ; free virtual = 43409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8527 ; free virtual = 43399 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8526 ; free virtual = 43398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8526 ; free virtual = 43398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8526 ; free virtual = 43398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8526 ; free virtual = 43398 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8524 ; free virtual = 43397 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 8524 ; free virtual = 43396 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1546.957 ; gain = 0.000 ; free physical = 8469 ; free virtual = 43341 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1546.957 ; gain = 0.000 ; free physical = 8408 ; free virtual = 43280 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21489 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 7585 ; free virtual = 42458 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 7544 ; free virtual = 42416 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 7527 ; free virtual = 42399 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 7524 ; free virtual = 42397 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 7523 ; free virtual = 42395 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 7514 ; free virtual = 42386 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 7503 ; free virtual = 42376 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 7509 ; free virtual = 42381 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 7506 ; free virtual = 42378 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 7484 ; free virtual = 42356 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 7486 ; free virtual = 42358 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 7458 ; free virtual = 42330 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 7423 ; free virtual = 42296 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 7423 ; free virtual = 42295 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 7395 ; free virtual = 42268 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7351 ; free virtual = 42224 Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7354 ; free virtual = 42226 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7353 ; free virtual = 42226 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7353 ; free virtual = 42225 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7352 ; free virtual = 42225 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7352 ; free virtual = 42225 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7327 ; free virtual = 42200 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 7322 ; free virtual = 42195 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 7311 ; free virtual = 42183 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 7347 ; free virtual = 42220 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 7347 ; free virtual = 42219 Writing placer database... Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 7338 ; free virtual = 42217 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Build RT Design | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 7187 ; free virtual = 42065 Loading site data... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 7135 ; free virtual = 42012 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 7134 ; free virtual = 42011 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1963.355 ; gain = 0.000 ; free physical = 7125 ; free virtual = 42002 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7077 ; free virtual = 41955 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6946 ; free virtual = 41823 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6917 ; free virtual = 41794 Phase 4 Rip-up And Reroute | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6916 ; free virtual = 41793 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6916 ; free virtual = 41793 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6916 ; free virtual = 41793 Phase 6 Post Hold Fix | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6916 ; free virtual = 41793 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15dc3536d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6913 ; free virtual = 41790 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15dc3536d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6922 ; free virtual = 41799 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15dc3536d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6927 ; free virtual = 41804 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6963 ; free virtual = 41840 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 6964 ; free virtual = 41841 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 6873 ; free virtual = 41752 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:19:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.023 ; gain = 338.105 ; free physical = 6852 ; free virtual = 41729 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:19:08 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 6821 ; free virtual = 41698 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2051.398 ; gain = 509.531 ; free physical = 7822 ; free virtual = 42700 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 7773 ; free virtual = 42651 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:251] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:7] Loading data files... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 7681 ; free virtual = 42559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 7674 ; free virtual = 42552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 7674 ; free virtual = 42552 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 7700 ; free virtual = 42577 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 7571 ; free virtual = 42453 Phase 1.3 Build Placer Netlist Model INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.398 ; gain = 509.531 ; free physical = 7428 ; free virtual = 42310 Phase 1.4 Constrain Clocks/Macros Loading data files... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.398 ; gain = 509.531 ; free physical = 7421 ; free virtual = 42302 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.398 ; gain = 509.531 ; free physical = 7394 ; free virtual = 42276 Phase 2 Final Placement Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.398 ; gain = 509.531 ; free physical = 7385 ; free virtual = 42267 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.398 ; gain = 509.531 ; free physical = 7385 ; free virtual = 42267 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2051.398 ; gain = 574.562 ; free physical = 7393 ; free virtual = 42275 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1904.445 ; gain = 0.000 ; free physical = 7377 ; free virtual = 42259 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:19:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2451.867 ; gain = 344.105 ; free physical = 7209 ; free virtual = 42091 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:19:16 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 8134 ; free virtual = 43016 Phase 1.4 Constrain Clocks/Macros Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 touch build/specimen_004/OK Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 8123 ; free virtual = 43005 /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 39 #of tags: 2 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 8156 ; free virtual = 43038 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 8160 ; free virtual = 43042 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 8160 ; free virtual = 43041 Phase 1.3 Build Placer Netlist Model Ending Placer Task | Checksum: 110ed1b10 report_drc (run_mandatory_drcs) completed successfully Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 8119 ; free virtual = 43001 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 8117 ; free virtual = 42999 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 7985 ; free virtual = 42867 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 7958 ; free virtual = 42840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7968 ; free virtual = 42850 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7779 ; free virtual = 42661 --------------------------------------------------------------------------------- Phase 1 Build RT Design Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7773 ; free virtual = 42655 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7767 ; free virtual = 42649 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7765 ; free virtual = 42647 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7762 ; free virtual = 42644 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7760 ; free virtual = 42642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7758 ; free virtual = 42639 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7744 ; free virtual = 42626 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 7739 ; free virtual = 42620 Loading site data... INFO: [Project 1-571] Translating synthesized netlist Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 7610 ; free virtual = 42492 Phase 1.4 Constrain Clocks/Macros Loading route data... Processing options... Creating bitmap... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 7584 ; free virtual = 42466 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.160 ; gain = 456.203 ; free physical = 7604 ; free virtual = 42485 Phase 2 Global Placement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 7600 ; free virtual = 42482 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 7576 ; free virtual = 42458 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 7575 ; free virtual = 42457 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 7575 ; free virtual = 42457 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 7566 ; free virtual = 42448 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 7566 ; free virtual = 42448 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.488 ; gain = 517.531 ; free physical = 7566 ; free virtual = 42448 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 7566 ; free virtual = 42448 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2063.930 ; gain = 45.668 ; free physical = 7316 ; free virtual = 42198 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.918 ; gain = 50.656 ; free physical = 7282 ; free virtual = 42163 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.918 ; gain = 50.656 ; free physical = 7281 ; free virtual = 42163 Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.973 ; gain = 60.711 ; free physical = 7226 ; free virtual = 42108 Phase 3 Initial Routing Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7203 ; free virtual = 42085 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7184 ; free virtual = 42066 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7179 ; free virtual = 42060 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7178 ; free virtual = 42060 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7178 ; free virtual = 42059 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7177 ; free virtual = 42059 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7177 ; free virtual = 42059 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7175 ; free virtual = 42057 Phase 3.2 Commit Most Macros & LUTRAMs Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 62.711 ; free physical = 7163 ; free virtual = 42045 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 7163 ; free virtual = 42045 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 7163 ; free virtual = 42045 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 7199 ; free virtual = 42081 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2121.762 ; gain = 135.516 ; free physical = 7199 ; free virtual = 42081 Writing placer database... Writing XDEF routing. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7189 ; free virtual = 42072 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 7188 ; free virtual = 42072 Phase 3.3 Area Swap Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7186 ; free virtual = 42069 Phase 3.4 Pipeline Register Optimization 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 7202 ; free virtual = 42084 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a INFO: [DRC 23-27] Running DRC with 8 threads Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7188 ; free virtual = 42072 Phase 3.5 Small Shape Detail Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 7382 ; free virtual = 42269 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1585d46d4 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 7404 ; free virtual = 42290 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7399 ; free virtual = 42285 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7396 ; free virtual = 42283 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7392 ; free virtual = 42278 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2129.961 ; gain = 30.758 ; free physical = 7387 ; free virtual = 42274 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7387 ; free virtual = 42274 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 7352 ; free virtual = 42238 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 7352 ; free virtual = 42238 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7358 ; free virtual = 42244 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7313 ; free virtual = 42200 Phase 4.3 Placer Reporting Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7291 ; free virtual = 42177 Phase 3 Initial Routing Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7267 ; free virtual = 42153 Phase 4.4 Final Placement Cleanup Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7284 ; free virtual = 42171 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7284 ; free virtual = 42171 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7282 ; free virtual = 42170 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7282 ; free virtual = 42170 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7282 ; free virtual = 42170 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7282 ; free virtual = 42170 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7282 ; free virtual = 42170 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7270 ; free virtual = 42160 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7269 ; free virtual = 42159 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7265 ; free virtual = 42155 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.004 ; gain = 54.801 ; free physical = 7299 ; free virtual = 42189 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2192.793 ; gain = 93.590 ; free physical = 7297 ; free virtual = 42188 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7297 ; free virtual = 42187 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:19:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2462.434 ; gain = 334.176 ; free physical = 7379 ; free virtual = 42269 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:19:32 2019... Writing placer database... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.211 ; gain = 560.254 ; free physical = 7498 ; free virtual = 42389 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 2107.211 ; gain = 639.957 ; free physical = 7509 ; free virtual = 42401 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:19:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.793 ; gain = 0.000 ; free physical = 8315 ; free virtual = 43229 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2452.871 ; gain = 342.105 ; free physical = 8325 ; free virtual = 43239 INFO: Launching helper process for spawning children vivado processes INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:19:35 2019... INFO: Helper process launched with PID 22756 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_005/OK INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 22885 Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 8590 ; free virtual = 43483 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: ec53b9f2 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.953 ; gain = 42.668 ; free physical = 8407 ; free virtual = 43300 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ec53b9f2 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 8371 ; free virtual = 43264 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ec53b9f2 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 8370 ; free virtual = 43263 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:139] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.246 ; gain = 60.961 ; free physical = 8282 ; free virtual = 43175 Phase 3 Initial Routing WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8270 ; free virtual = 43164 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8250 ; free virtual = 43143 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8220 ; free virtual = 43113 Phase 4 Rip-up And Reroute | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8237 ; free virtual = 43130 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8234 ; free virtual = 43127 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8234 ; free virtual = 43127 Phase 6 Post Hold Fix | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8234 ; free virtual = 43127 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8276 ; free virtual = 43170 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8275 ; free virtual = 43169 --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 8269 ; free virtual = 43163 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 8272 ; free virtual = 43165 Phase 9 Depositing Routes INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 9 Depositing Routes | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.246 ; gain = 65.961 ; free physical = 8247 ; free virtual = 43141 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.246 ; gain = 65.961 ; free physical = 8280 ; free virtual = 43174 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2131.035 ; gain = 136.766 ; free physical = 8278 ; free virtual = 43171 Writing placer database... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 8168 ; free virtual = 43061 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2131.035 ; gain = 0.000 ; free physical = 7957 ; free virtual = 42854 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 7923 ; free virtual = 42817 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d38ee6f1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7897 ; free virtual = 42791 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7893 ; free virtual = 42787 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7893 ; free virtual = 42787 Phase 1 Placer Initialization | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7892 ; free virtual = 42786 Phase 2 Global Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... Loading site data... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 7599 ; free virtual = 42493 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 2 Global Placement | Checksum: 262ca559a Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7612 ; free virtual = 42506 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 262ca559a Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7605 ; free virtual = 42500 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23e660b1f Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7588 ; free virtual = 42483 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21840e8ea Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7563 ; free virtual = 42457 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e1f5494f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7546 ; free virtual = 42440 Phase 3.5 Small Shape Detail Placement Loading data files... Phase 3.5 Small Shape Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7521 ; free virtual = 42415 Phase 3.6 Re-assign LUT pins Writing bitstream ./design.bit... Phase 3.6 Re-assign LUT pins | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7518 ; free virtual = 42412 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7517 ; free virtual = 42412 Phase 3 Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7515 ; free virtual = 42411 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7509 ; free virtual = 42406 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7509 ; free virtual = 42407 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7520 ; free virtual = 42418 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7531 ; free virtual = 42429 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7548 ; free virtual = 42446 Ending Placer Task | Checksum: 1cc0c8886 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 7578 ; free virtual = 42476 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 7579 ; free virtual = 42477 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7813 ; free virtual = 42712 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7809 ; free virtual = 42708 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7809 ; free virtual = 42708 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7802 ; free virtual = 42701 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 7738 ; free virtual = 42637 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 7707 ; free virtual = 42606 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e76cdf7c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7693 ; free virtual = 42592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23684 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7590 ; free virtual = 42488 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7589 ; free virtual = 42487 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7587 ; free virtual = 42486 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7586 ; free virtual = 42484 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7585 ; free virtual = 42483 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7584 ; free virtual = 42483 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7584 ; free virtual = 42482 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7580 ; free virtual = 42479 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 7582 ; free virtual = 42481 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:19:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2461.867 ; gain = 340.105 ; free physical = 7545 ; free virtual = 42443 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:20:00 2019... Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23786 Phase 1 Build RT Design | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2136.082 ; gain = 52.668 ; free physical = 8555 ; free virtual = 43458 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.070 ; gain = 61.656 ; free physical = 8480 ; free virtual = 43383 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.070 ; gain = 61.656 ; free physical = 8478 ; free virtual = 43382 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 8383 ; free virtual = 43286 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:20:04 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2533.898 ; gain = 341.105 ; free physical = 8401 ; free virtual = 43305 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 8401 ; free virtual = 43304 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:20:04 2019... --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8421 ; free virtual = 43324 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 8428 ; free virtual = 43331 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 8446 ; free virtual = 43349 Phase 3 Initial Routing Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Bitstream size: 4243411 bytes Phase 3 Initial Routing | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9426 ; free virtual = 44329 Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9423 ; free virtual = 44326 Phase 4 Rip-up And Reroute | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9422 ; free virtual = 44325 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9421 ; free virtual = 44324 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9419 ; free virtual = 44322 Loading site data... Phase 6 Post Hold Fix | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9414 ; free virtual = 44317 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9402 ; free virtual = 44306 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9400 ; free virtual = 44303 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9400 ; free virtual = 44303 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9399 ; free virtual = 44302 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9399 ; free virtual = 44302 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9398 ; free virtual = 44302 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9399 ; free virtual = 44303 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9399 ; free virtual = 44303 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9399 ; free virtual = 44302 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9398 ; free virtual = 44302 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9398 ; free virtual = 44301 INFO: [Project 1-571] Translating synthesized netlist Loading route data... Starting Placer Task Processing options... Creating bitmap... INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 9337 ; free virtual = 44240 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15fdaa0f7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 9329 ; free virtual = 44232 Phase 9 Depositing Routes | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9319 ; free virtual = 44222 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.500 ; gain = 97.086 ; free physical = 9362 ; free virtual = 44265 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2219.289 ; gain = 167.891 ; free physical = 9361 ; free virtual = 44264 Writing placer database... Phase 1 Build RT Design | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.074 ; gain = 51.668 ; free physical = 9332 ; free virtual = 44237 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2.1 Fix Topology Constraints | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2146.062 ; gain = 61.656 ; free physical = 9376 ; free virtual = 44285 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2146.062 ; gain = 61.656 ; free physical = 9374 ; free virtual = 44283 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9290 ; free virtual = 44203 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9279 ; free virtual = 44197 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9274 ; free virtual = 44193 Phase 4 Rip-up And Reroute | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9273 ; free virtual = 44192 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9273 ; free virtual = 44192 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9272 ; free virtual = 44191 Phase 6 Post Hold Fix | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9272 ; free virtual = 44191 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18b270a8f Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9257 ; free virtual = 44178 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18b270a8f Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9255 ; free virtual = 44176 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9249 ; free virtual = 44171 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 18b270a8f Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9240 ; free virtual = 44166 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2182.492 ; gain = 98.086 ; free physical = 9281 ; free virtual = 44207 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2221.281 ; gain = 168.891 ; free physical = 9281 ; free virtual = 44207 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Writing placer database... Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2219.289 ; gain = 0.000 ; free physical = 9254 ; free virtual = 44187 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.172 ; gain = 43.668 ; free physical = 9231 ; free virtual = 44165 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 9189 ; free virtual = 44124 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2073.160 ; gain = 50.656 ; free physical = 9188 ; free virtual = 44123 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2083.465 ; gain = 60.961 ; free physical = 9142 ; free virtual = 44081 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 9135 ; free virtual = 44074 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2219.289 ; gain = 0.000 ; free physical = 9140 ; free virtual = 44054 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 9134 ; free virtual = 44049 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 9126 ; free virtual = 44041 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 9125 ; free virtual = 44040 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 9123 ; free virtual = 44038 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 9122 ; free virtual = 44037 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.465 ; gain = 61.961 ; free physical = 9121 ; free virtual = 44037 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 9126 ; free virtual = 44042 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 9135 ; free virtual = 44051 Phase 9 Depositing Routes 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 9162 ; free virtual = 44079 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9145 ; free virtual = 44061 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 9122 ; free virtual = 44039 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.465 ; gain = 65.961 ; free physical = 9155 ; free virtual = 44073 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2127.254 ; gain = 136.766 ; free physical = 9150 ; free virtual = 44068 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9164 ; free virtual = 44082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9168 ; free virtual = 44087 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9178 ; free virtual = 44097 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 9182 ; free virtual = 44106 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 9002 ; free virtual = 43927 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 9001 ; free virtual = 43927 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2221.281 ; gain = 0.000 ; free physical = 9039 ; free virtual = 43975 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2221.281 ; gain = 0.000 ; free physical = 9004 ; free virtual = 43913 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2129.434 ; gain = 22.223 ; free physical = 9069 ; free virtual = 43983 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.422 ; gain = 28.211 ; free physical = 9044 ; free virtual = 43959 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.422 ; gain = 28.211 ; free physical = 9044 ; free virtual = 43958 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:16] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 8950 ; free virtual = 43865 Phase 3 Initial Routing WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:7] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9016 ; free virtual = 43930 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9012 ; free virtual = 43927 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9012 ; free virtual = 43927 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9011 ; free virtual = 43927 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9011 ; free virtual = 43926 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9011 ; free virtual = 43926 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 8989 ; free virtual = 43910 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 8988 ; free virtual = 43908 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 8983 ; free virtual = 43904 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2154.477 ; gain = 47.266 ; free physical = 9015 ; free virtual = 43936 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2193.266 ; gain = 86.055 ; free physical = 9013 ; free virtual = 43934 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9013 ; free virtual = 43929 --------------------------------------------------------------------------------- Writing placer database... Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8983 ; free virtual = 43902 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 8983 ; free virtual = 43902 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:20:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.141 ; gain = 339.105 ; free physical = 8818 ; free virtual = 43744 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:20:22 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 8937 ; free virtual = 43863 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 8898 ; free virtual = 43825 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9181 ; free virtual = 44108 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9657 ; free virtual = 44592 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9652 ; free virtual = 44587 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9643 ; free virtual = 44578 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9642 ; free virtual = 44578 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9643 ; free virtual = 44579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9644 ; free virtual = 44579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9646 ; free virtual = 44582 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9652 ; free virtual = 44588 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 9653 ; free virtual = 44589 INFO: [Project 1-571] Translating synthesized netlist Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.266 ; gain = 0.000 ; free physical = 9568 ; free virtual = 44508 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 9565 ; free virtual = 44505 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24114 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 8923 ; free virtual = 43841 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dac8b64b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8795 ; free virtual = 43713 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8772 ; free virtual = 43690 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8764 ; free virtual = 43682 Phase 1 Placer Initialization | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 8755 ; free virtual = 43673 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 8709 ; free virtual = 43627 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Loading data files... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8617 ; free virtual = 43535 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8533 ; free virtual = 43451 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1464.715 ; gain = 0.000 ; free physical = 8502 ; free virtual = 43420 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1464.715 ; gain = 0.000 ; free physical = 8503 ; free virtual = 43422 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24756 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8427 ; free virtual = 43346 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... Loading route data... Processing options... Creating bitmap... Phase 2 Global Placement | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8294 ; free virtual = 43213 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8291 ; free virtual = 43209 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22a14ef89 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8288 ; free virtual = 43206 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8272 ; free virtual = 43190 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8249 ; free virtual = 43167 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 203efcd54 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8257 ; free virtual = 43175 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1cda42db9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8236 ; free virtual = 43154 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8215 ; free virtual = 43134 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8191 ; free virtual = 43109 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8208 ; free virtual = 43126 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8206 ; free virtual = 43124 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8205 ; free virtual = 43123 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8204 ; free virtual = 43123 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 8205 ; free virtual = 43124 INFO: [Project 1-571] Translating synthesized netlist Phase 3.5 Small Shape Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8117 ; free virtual = 43036 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8114 ; free virtual = 43033 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8143 ; free virtual = 43062 Phase 3 Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8142 ; free virtual = 43061 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8142 ; free virtual = 43060 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8134 ; free virtual = 43052 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8130 ; free virtual = 43048 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8126 ; free virtual = 43044 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8120 ; free virtual = 43039 Ending Placer Task | Checksum: 1c8c94742 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.539 ; gain = 595.574 ; free physical = 8126 ; free virtual = 43045 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.539 ; gain = 659.605 ; free physical = 8115 ; free virtual = 43034 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Creating bitstream... WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 7729 ; free virtual = 42647 --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4299e38 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 7616 ; free virtual = 42534 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7446 ; free virtual = 42364 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7444 ; free virtual = 42363 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7444 ; free virtual = 42363 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7444 ; free virtual = 42363 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7444 ; free virtual = 42363 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7446 ; free virtual = 42364 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 7446 ; free virtual = 42364 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 7422 ; free virtual = 42345 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 7663 ; free virtual = 42586 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 7661 ; free virtual = 42584 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 7695 ; free virtual = 42617 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:20:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2462.430 ; gain = 335.176 ; free physical = 7432 ; free virtual = 42355 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:20:42 2019... Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 7431 ; free virtual = 42354 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8138 ; free virtual = 43061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8132 ; free virtual = 43056 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8131 ; free virtual = 43055 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8128 ; free virtual = 43051 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15ca2bf97 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8038 ; free virtual = 42962 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15ca2bf97 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8001 ; free virtual = 42925 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15ca2bf97 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8001 ; free virtual = 42925 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Creating bitstream... 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:49 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 7956 ; free virtual = 42880 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: fe41f556 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7956 ; free virtual = 42879 Phase 3 Initial Routing Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7901 ; free virtual = 42824 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7897 ; free virtual = 42821 Phase 4 Rip-up And Reroute | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7897 ; free virtual = 42820 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7895 ; free virtual = 42819 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7895 ; free virtual = 42819 Phase 6 Post Hold Fix | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7895 ; free virtual = 42818 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 7886 ; free virtual = 42810 --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7882 ; free virtual = 42805 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7880 ; free virtual = 42804 Phase 9 Depositing Routes Creating bitstream... Phase 9 Depositing Routes | Checksum: e279f4d5 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7878 ; free virtual = 42802 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 7918 ; free virtual = 42841 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2140.016 ; gain = 47.473 ; free physical = 7917 ; free virtual = 42841 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 7903 ; free virtual = 42827 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing placer database... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7899 ; free virtual = 42823 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 7881 ; free virtual = 42807 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25082 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.961 ; gain = 0.000 ; free physical = 7835 ; free virtual = 42759 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.82 . Memory (MB): peak = 1549.961 ; gain = 0.000 ; free physical = 7802 ; free virtual = 42726 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7859 ; free virtual = 42783 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7860 ; free virtual = 42785 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7860 ; free virtual = 42785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7860 ; free virtual = 42785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7860 ; free virtual = 42785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7859 ; free virtual = 42785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7859 ; free virtual = 42785 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 7859 ; free virtual = 42785 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 7861 ; free virtual = 42786 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Vivado 12-1842] Bitgen Completed Successfully. Creating bitstream... INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 7981 ; free virtual = 42914 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 7941 ; free virtual = 42873 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 7937 ; free virtual = 42869 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 7934 ; free virtual = 42866 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 7933 ; free virtual = 42866 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 7933 ; free virtual = 42866 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 7933 ; free virtual = 42865 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1932.246 ; gain = 467.531 ; free physical = 7932 ; free virtual = 42865 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 7932 ; free virtual = 42864 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 7900 ; free virtual = 42833 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 7896 ; free virtual = 42828 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:20:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2532.371 ; gain = 339.105 ; free physical = 7870 ; free virtual = 42807 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:20:58 2019... Bitstream size: 4243411 bytes INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9185 ; free virtual = 44121 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9182 ; free virtual = 44119 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9181 ; free virtual = 44117 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9180 ; free virtual = 44116 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9179 ; free virtual = 44115 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9178 ; free virtual = 44115 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:20:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9178 ; free virtual = 44114 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9177 ; free virtual = 44113 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9183 ; free virtual = 44119 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:47 . Memory (MB): peak = 2607.449 ; gain = 388.160 ; free physical = 9185 ; free virtual = 44121 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:20:59 2019... INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 9202 ; free virtual = 44137 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 10080 ; free virtual = 45016 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 10088 ; free virtual = 45024 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 10085 ; free virtual = 45027 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:21:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:45 . Memory (MB): peak = 2609.441 ; gain = 388.160 ; free physical = 10061 ; free virtual = 45003 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:21:02 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 10952 ; free virtual = 45894 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 10972 ; free virtual = 45914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 11013 ; free virtual = 45960 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 11013 ; free virtual = 45960 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 10959 ; free virtual = 45906 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 10884 ; free virtual = 45831 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 10876 ; free virtual = 45823 Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25429 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 10074 ; free virtual = 45021 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 10114 ; free virtual = 45061 --------------------------------------------------------------------------------- Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 10023 ; free virtual = 44970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 10023 ; free virtual = 44971 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.164 ; gain = 453.203 ; free physical = 10050 ; free virtual = 44997 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9964 ; free virtual = 44911 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9963 ; free virtual = 44910 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9962 ; free virtual = 44910 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9962 ; free virtual = 44910 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9962 ; free virtual = 44909 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9961 ; free virtual = 44909 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9961 ; free virtual = 44908 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9960 ; free virtual = 44907 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 9961 ; free virtual = 44908 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10166 ; free virtual = 45117 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.164 ; gain = 453.203 ; free physical = 10114 ; free virtual = 45065 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 453.203 ; free physical = 10017 ; free virtual = 44969 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 453.203 ; free physical = 10027 ; free virtual = 44979 Phase 2 Global Placement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9970 ; free virtual = 44922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9911 ; free virtual = 44863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9907 ; free virtual = 44859 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9850 ; free virtual = 44801 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:21:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Timing 38-35] Done setting XDC timing constraints. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 2475.121 ; gain = 335.105 ; free physical = 9652 ; free virtual = 44604 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:21:20 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 9641 ; free virtual = 44593 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 9786 ; free virtual = 44737 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 10268 ; free virtual = 45220 Phase 1.4 Constrain Clocks/Macros INFO: Launching helper process for spawning children vivado processes Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 10533 ; free virtual = 45485 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 10592 ; free virtual = 45543 Phase 2 Final Placement Cleanup INFO: Helper process launched with PID 26146 Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 10594 ; free virtual = 45545 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 514.531 ; free physical = 10595 ; free virtual = 45546 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 10595 ; free virtual = 45546 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Config size: 1060815 words Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10467 ; free virtual = 45419 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 10477 ; free virtual = 45429 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10451 ; free virtual = 45403 Phase 3.2 Commit Most Macros & LUTRAMs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10494 ; free virtual = 45447 Phase 3.3 Area Swap Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10447 ; free virtual = 45399 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10385 ; free virtual = 45337 Phase 3.5 Small Shape Detail Placement Phase 1 Build RT Design | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 10388 ; free virtual = 45340 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 10368 ; free virtual = 45321 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2084.539 ; gain = 0.000 ; free physical = 10366 ; free virtual = 45318 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 10341 ; free virtual = 45293 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 10317 ; free virtual = 45270 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4ae2ab4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10142 ; free virtual = 45095 Phase 3 Initial Routing INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26352 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10157 ; free virtual = 45109 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1899.195 ; gain = 0.000 ; free physical = 10154 ; free virtual = 45106 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10151 ; free virtual = 45104 Phase 4 Rip-up And Reroute | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10151 ; free virtual = 45103 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10149 ; free virtual = 45102 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10149 ; free virtual = 45101 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 6 Post Hold Fix | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10149 ; free virtual = 45101 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1 Build RT Design | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 10103 ; free virtual = 45056 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 130e541f3 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10097 ; free virtual = 45050 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130e541f3 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10096 ; free virtual = 45048 Phase 9 Depositing Routes Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 10111 ; free virtual = 45064 Phase 1.3 Build Placer Netlist Model Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 10086 ; free virtual = 45038 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 10086 ; free virtual = 45038 Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 10083 ; free virtual = 45035 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Phase 9 Depositing Routes | Checksum: 130e541f3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 10083 ; free virtual = 45035 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10083 ; free virtual = 45035 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2101.227 ; gain = 16.688 ; free physical = 10120 ; free virtual = 45072 Routing Is Done. Phase 1 Placer Initialization | Checksum: bca60bcf 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 10120 ; free virtual = 45072 route_design completed successfully Phase 2 Final Placement Cleanup route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2140.016 ; gain = 55.477 ; free physical = 10120 ; free virtual = 45072 Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 10119 ; free virtual = 45071 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.238 ; gain = 515.531 ; free physical = 10117 ; free virtual = 45069 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.238 ; gain = 581.562 ; free physical = 10117 ; free virtual = 45069 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10103 ; free virtual = 45056 Phase 3.6 Re-assign LUT pins Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 10095 ; free virtual = 45050 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10091 ; free virtual = 45046 Phase 3 Initial Routing INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10076 ; free virtual = 45029 Phase 3.7 Pipeline Register Optimization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10063 ; free virtual = 45015 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10058 ; free virtual = 45010 Phase 4 Rip-up And Reroute | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10058 ; free virtual = 45010 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10057 ; free virtual = 45010 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10056 ; free virtual = 45009 Phase 6 Post Hold Fix | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10056 ; free virtual = 45009 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10031 ; free virtual = 44984 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 10026 ; free virtual = 44979 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 10025 ; free virtual = 44977 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 10022 ; free virtual = 44974 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 10053 ; free virtual = 45006 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 10052 ; free virtual = 45005 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 10036 ; free virtual = 44989 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 10023 ; free virtual = 44977 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 9983 ; free virtual = 44936 Phase 4.2 Post Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 9990 ; free virtual = 44943 Phase 4.3 Placer Reporting INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 9965 ; free virtual = 44919 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 9980 ; free virtual = 44933 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 9947 ; free virtual = 44900 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26450 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.211 ; gain = 549.250 ; free physical = 9980 ; free virtual = 44936 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.211 ; gain = 631.953 ; free physical = 9978 ; free virtual = 44936 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9929 ; free virtual = 44882 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9910 ; free virtual = 44863 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9903 ; free virtual = 44856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9872 ; free virtual = 44825 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9884 ; free virtual = 44837 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9881 ; free virtual = 44834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9880 ; free virtual = 44833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9878 ; free virtual = 44832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9877 ; free virtual = 44830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9876 ; free virtual = 44829 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9871 ; free virtual = 44824 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 9871 ; free virtual = 44824 INFO: [Project 1-571] Translating synthesized netlist Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9595 ; free virtual = 44548 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9385 ; free virtual = 44338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9379 ; free virtual = 44333 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9378 ; free virtual = 44332 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9360 ; free virtual = 44314 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9247 ; free virtual = 44201 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 8878 ; free virtual = 43832 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8760 ; free virtual = 43713 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8745 ; free virtual = 43699 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 8723 ; free virtual = 43677 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: 154656e26 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 8391 ; free virtual = 43344 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 154656e26 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 8346 ; free virtual = 43299 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 154656e26 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 8342 ; free virtual = 43295 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8170 ; free virtual = 43123 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8065 ; free virtual = 43019 Loading site data... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8061 ; free virtual = 43014 Phase 4 Rip-up And Reroute | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8061 ; free virtual = 43014 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8060 ; free virtual = 43014 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8060 ; free virtual = 43014 Phase 6 Post Hold Fix | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 8060 ; free virtual = 43014 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 790be677 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8034 ; free virtual = 42988 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 790be677 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 8032 ; free virtual = 42986 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 790be677 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 8031 ; free virtual = 42985 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 8062 ; free virtual = 43016 Routing Is Done. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 8061 ; free virtual = 43015 INFO: [Timing 38-35] Done setting XDC timing constraints. Writing placer database... Writing XDEF routing. Loading route data... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 8022 ; free virtual = 42977 Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.234 ; gain = 0.000 ; free physical = 7971 ; free virtual = 42925 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 7910 ; free virtual = 42864 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 7881 ; free virtual = 42836 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 7882 ; free virtual = 42836 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 7891 ; free virtual = 42845 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7890 ; free virtual = 42844 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Loading route data... --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- Processing options... --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Creating bitmap... --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 7890 ; free virtual = 42844 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 7910 ; free virtual = 42864 Phase 2 Final Placement Cleanup Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 7911 ; free virtual = 42865 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.277 ; gain = 510.531 ; free physical = 7911 ; free virtual = 42865 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 576.562 ; free physical = 7911 ; free virtual = 42865 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26608 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7854 ; free virtual = 42808 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7852 ; free virtual = 42806 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7850 ; free virtual = 42804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7850 ; free virtual = 42804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7850 ; free virtual = 42804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7850 ; free virtual = 42803 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7849 ; free virtual = 42803 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 7849 ; free virtual = 42803 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7851 ; free virtual = 42805 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing bitstream ./design.bit... Loading data files... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 7899 ; free virtual = 42858 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 7778 ; free virtual = 42737 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1333.102 ; gain = 237.184 ; free physical = 7777 ; free virtual = 42737 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 7803 ; free virtual = 42763 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 7902 ; free virtual = 42866 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:21:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 7913 ; free virtual = 42876 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2453.867 ; gain = 343.105 ; free physical = 7914 ; free virtual = 42878 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:21:54 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 8033 ; free virtual = 42998 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 8830 ; free virtual = 43796 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:83] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 8872 ; free virtual = 43862 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 8866 ; free virtual = 43857 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 8865 ; free virtual = 43856 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:21:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 8776 ; free virtual = 43766 --------------------------------------------------------------------------------- 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.121 ; gain = 334.105 ; free physical = 8777 ; free virtual = 43768 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:21:58 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 8795 ; free virtual = 43766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 8794 ; free virtual = 43765 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1341.070 ; gain = 245.152 ; free physical = 9643 ; free virtual = 44614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 9282 ; free virtual = 44254 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9259 ; free virtual = 44230 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9252 ; free virtual = 44224 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9244 ; free virtual = 44215 Loading route data... Processing options... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Creating bitmap... Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9232 ; free virtual = 44204 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9219 ; free virtual = 44191 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 9218 ; free virtual = 44190 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 9217 ; free virtual = 44189 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1349.102 ; gain = 253.184 ; free physical = 9192 ; free virtual = 44164 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1349.102 ; gain = 253.184 ; free physical = 9181 ; free virtual = 44153 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9090 ; free virtual = 44061 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 1347.066 ; gain = 251.152 ; free physical = 9028 ; free virtual = 44000 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9005 ; free virtual = 43977 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9002 ; free virtual = 43974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 8993 ; free virtual = 43965 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 8988 ; free virtual = 43963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9015 ; free virtual = 43990 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9060 ; free virtual = 44035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9080 ; free virtual = 44056 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9082 ; free virtual = 44058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 9083 ; free virtual = 44059 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.078 ; gain = 261.160 ; free physical = 9080 ; free virtual = 44056 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1357.086 ; gain = 261.160 ; free physical = 9099 ; free virtual = 44075 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9138 ; free virtual = 44114 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9287 ; free virtual = 44263 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44262 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 9288 ; free virtual = 44264 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1355.098 ; gain = 259.184 ; free physical = 9273 ; free virtual = 44249 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1355.098 ; gain = 259.184 ; free physical = 9267 ; free virtual = 44242 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2062.930 ; gain = 44.668 ; free physical = 9174 ; free virtual = 44150 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9118 ; free virtual = 44094 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.918 ; gain = 49.656 ; free physical = 9110 ; free virtual = 44086 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.918 ; gain = 49.656 ; free physical = 9109 ; free virtual = 44085 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:22:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2452.867 ; gain = 342.105 ; free physical = 9158 ; free virtual = 44134 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.922 ; gain = 43.668 ; free physical = 9158 ; free virtual = 44134 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:22:09 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.910 ; gain = 48.656 ; free physical = 9135 ; free virtual = 44111 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.910 ; gain = 48.656 ; free physical = 9136 ; free virtual = 44112 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2077.973 ; gain = 59.711 ; free physical = 9197 ; free virtual = 44173 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 9814 ; free virtual = 44790 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2078.965 ; gain = 59.711 ; free physical = 9852 ; free virtual = 44828 Phase 3 Initial Routing Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 10117 ; free virtual = 45092 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 10117 ; free virtual = 45093 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 10120 ; free virtual = 45096 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 10122 ; free virtual = 45098 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 10123 ; free virtual = 45098 Bitstream size: 4243411 bytes Phase 7 Route finalize Config size: 1060815 words Number of configuration frames: 9996 DONE Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 10084 ; free virtual = 45060 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 10081 ; free virtual = 45057 Phase 9 Depositing Routes touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10076 ; free virtual = 45052 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10065 ; free virtual = 45041 Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 10065 ; free virtual = 45041 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10073 ; free virtual = 45048 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10096 ; free virtual = 45072 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.973 ; gain = 64.711 ; free physical = 10098 ; free virtual = 45074 Routing Is Done. Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10098 ; free virtual = 45074 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2121.762 ; gain = 135.516 ; free physical = 10099 ; free virtual = 45075 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10092 ; free virtual = 45068 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.965 ; gain = 61.711 ; free physical = 10082 ; free virtual = 45057 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.965 ; gain = 63.711 ; free physical = 10079 ; free virtual = 45055 Phase 9 Depositing Routes Writing placer database... Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.965 ; gain = 63.711 ; free physical = 10034 ; free virtual = 45010 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.965 ; gain = 63.711 ; free physical = 10061 ; free virtual = 45037 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2121.754 ; gain = 134.516 ; free physical = 10061 ; free virtual = 45037 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 10039 ; free virtual = 45017 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 10037 ; free virtual = 45015 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 10020 ; free virtual = 44999 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2121.754 ; gain = 0.000 ; free physical = 10004 ; free virtual = 44982 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9959 ; free virtual = 44936 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9884 ; free virtual = 44861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9878 ; free virtual = 44855 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9863 ; free virtual = 44839 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9858 ; free virtual = 44835 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.074 ; gain = 267.160 ; free physical = 9845 ; free virtual = 44822 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1363.082 ; gain = 267.160 ; free physical = 9839 ; free virtual = 44816 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 9627 ; free virtual = 44604 INFO: [Timing 38-35] Done setting XDC timing constraints. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 9642 ; free virtual = 44618 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9543 ; free virtual = 44520 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9535 ; free virtual = 44512 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9602 ; free virtual = 44579 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9597 ; free virtual = 44574 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9587 ; free virtual = 44564 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9569 ; free virtual = 44545 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 9567 ; free virtual = 44544 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2129.969 ; gain = 30.758 ; free physical = 9552 ; free virtual = 44529 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Starting Placer Task Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 9541 ; free virtual = 44517 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.957 ; gain = 36.746 ; free physical = 9542 ; free virtual = 44519 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.957 ; gain = 36.746 ; free physical = 9542 ; free virtual = 44519 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16bd26d57 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 9533 ; free virtual = 44510 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9457 ; free virtual = 44434 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9367 ; free virtual = 44344 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9360 ; free virtual = 44336 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9359 ; free virtual = 44336 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9359 ; free virtual = 44336 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9359 ; free virtual = 44335 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9358 ; free virtual = 44335 Phase 7 Route finalize Starting Routing Task Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9349 ; free virtual = 44326 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9350 ; free virtual = 44326 Phase 9 Depositing Routes Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9348 ; free virtual = 44325 Phase 1 Build RT Design INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.012 ; gain = 55.801 ; free physical = 9382 ; free virtual = 44359 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 2193.801 ; gain = 94.590 ; free physical = 9381 ; free virtual = 44358 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... Loading data files... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.801 ; gain = 0.000 ; free physical = 8954 ; free virtual = 43954 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27054 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27117 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... Loading data files... Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.961 ; gain = 42.668 ; free physical = 8079 ; free virtual = 43057 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.949 ; gain = 49.656 ; free physical = 8040 ; free virtual = 43018 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.949 ; gain = 49.656 ; free physical = 8039 ; free virtual = 43017 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11706d75b Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2087.379 ; gain = 62.086 ; free physical = 7968 ; free virtual = 42946 Phase 3 Initial Routing INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7971 ; free virtual = 42949 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7995 ; free virtual = 42973 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 7996 ; free virtual = 42974 Phase 4 Rip-up And Reroute | Checksum: 11706d75b Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7996 ; free virtual = 42974 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7996 ; free virtual = 42974 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7995 ; free virtual = 42974 Phase 6 Post Hold Fix | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7995 ; free virtual = 42974 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 7 Route finalize INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7990 ; free virtual = 42968 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.379 ; gain = 67.086 ; free physical = 7990 ; free virtual = 42968 Phase 9 Depositing Routes Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.379 ; gain = 67.086 ; free physical = 7978 ; free virtual = 42957 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.379 ; gain = 67.086 ; free physical = 8016 ; free virtual = 42994 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2131.168 ; gain = 137.891 ; free physical = 8015 ; free virtual = 42993 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.77 . Memory (MB): peak = 2131.168 ; gain = 0.000 ; free physical = 7927 ; free virtual = 42909 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 7894 ; free virtual = 42876 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1550.867 ; gain = 0.000 ; free physical = 7817 ; free virtual = 42796 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.87 . Memory (MB): peak = 1550.867 ; gain = 0.000 ; free physical = 7733 ; free virtual = 42712 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] Creating bitstream... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 7481 ; free virtual = 42460 --------------------------------------------------------------------------------- Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27214 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 7315 ; free virtual = 42294 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1487277ac Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 7238 ; free virtual = 42217 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 7228 ; free virtual = 42209 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 7213 ; free virtual = 42195 Phase 1 Placer Initialization | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 7209 ; free virtual = 42191 Phase 2 Global Placement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 7376 ; free virtual = 42359 --------------------------------------------------------------------------------- Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 7527 ; free virtual = 42510 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 7526 ; free virtual = 42509 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 7528 ; free virtual = 42511 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:13 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 7510 ; free virtual = 42494 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading site data... Loading route data... Processing options... Creating bitmap... Phase 2 Global Placement | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7607 ; free virtual = 42595 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7606 ; free virtual = 42594 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24340a58a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7607 ; free virtual = 42594 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d1b8355 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7606 ; free virtual = 42594 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6cfe3ba Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7606 ; free virtual = 42594 Phase 3.5 Small Shape Detail Placement Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1560.855 ; gain = 0.000 ; free physical = 7581 ; free virtual = 42568 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.66 . Memory (MB): peak = 1560.855 ; gain = 0.000 ; free physical = 7579 ; free virtual = 42567 Phase 3.5 Small Shape Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7578 ; free virtual = 42566 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7578 ; free virtual = 42566 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7578 ; free virtual = 42565 Phase 3 Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7577 ; free virtual = 42565 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7577 ; free virtual = 42564 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7567 ; free virtual = 42555 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7567 ; free virtual = 42554 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7567 ; free virtual = 42554 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7567 ; free virtual = 42554 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:22:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Ending Placer Task | Checksum: 163bdd4e6 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 7587 ; free virtual = 42574 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.551 ; gain = 667.609 ; free physical = 7587 ; free virtual = 42574 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2462.867 ; gain = 341.105 ; free physical = 7593 ; free virtual = 42580 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:22:43 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:22:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2461.859 ; gain = 340.105 ; free physical = 7672 ; free virtual = 42660 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:22:43 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 7f1e2bdc ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9544 ; free virtual = 44533 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.176 ; gain = 44.668 ; free physical = 9481 ; free virtual = 44470 Writing bitstream ./design.bit... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 9446 ; free virtual = 44436 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 9445 ; free virtual = 44436 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9657 ; free virtual = 44650 Phase 3 Initial Routing INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9712 ; free virtual = 44705 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9673 ; free virtual = 44665 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9672 ; free virtual = 44664 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9665 ; free virtual = 44657 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9659 ; free virtual = 44652 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9659 ; free virtual = 44651 Phase 5 Delay and Skew Optimization --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9656 ; free virtual = 44649 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9656 ; free virtual = 44649 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9655 ; free virtual = 44648 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.594 ; gain = 63.086 ; free physical = 9613 ; free virtual = 44606 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2087.594 ; gain = 65.086 ; free physical = 9607 ; free virtual = 44600 Phase 9 Depositing Routes WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.594 ; gain = 66.086 ; free physical = 9620 ; free virtual = 44613 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.594 ; gain = 66.086 ; free physical = 9658 ; free virtual = 44651 Routing Is Done. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2127.383 ; gain = 136.891 ; free physical = 9657 ; free virtual = 44650 Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9694 ; free virtual = 44688 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9686 ; free virtual = 44681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9684 ; free virtual = 44679 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2127.383 ; gain = 0.000 ; free physical = 9681 ; free virtual = 44678 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9691 ; free virtual = 44688 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9737 ; free virtual = 44731 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9735 ; free virtual = 44730 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9734 ; free virtual = 44729 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9730 ; free virtual = 44726 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9729 ; free virtual = 44725 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9728 ; free virtual = 44724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9727 ; free virtual = 44723 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9721 ; free virtual = 44717 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 9720 ; free virtual = 44717 INFO: [Project 1-571] Translating synthesized netlist Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9602 ; free virtual = 44597 --------------------------------------------------------------------------------- Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:22:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.406 ; gain = 338.605 ; free physical = 9560 ; free virtual = 44575 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:22:50 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 10547 ; free virtual = 45542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 DONE --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 10547 ; free virtual = 45542 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 10149 ; free virtual = 45145 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 9859 ; free virtual = 44856 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 9849 ; free virtual = 44846 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9801 ; free virtual = 44797 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9779 ; free virtual = 44775 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9765 ; free virtual = 44761 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9754 ; free virtual = 44751 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 9678 ; free virtual = 44675 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9661 ; free virtual = 44657 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9661 ; free virtual = 44657 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9660 ; free virtual = 44657 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9660 ; free virtual = 44657 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9660 ; free virtual = 44656 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9659 ; free virtual = 44656 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9659 ; free virtual = 44656 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9655 ; free virtual = 44652 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9653 ; free virtual = 44650 Creating bitstream... INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.398 ; gain = 501.531 ; free physical = 9535 ; free virtual = 44532 Phase 1.3 Build Placer Netlist Model No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1338.098 ; gain = 242.184 ; free physical = 9446 ; free virtual = 44443 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1338.098 ; gain = 242.184 ; free physical = 9392 ; free virtual = 44390 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.172 ; gain = 44.668 ; free physical = 9400 ; free virtual = 44400 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2075.160 ; gain = 51.656 ; free physical = 9416 ; free virtual = 44416 Phase 2.2 Pre Route Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2075.160 ; gain = 51.656 ; free physical = 9418 ; free virtual = 44419 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9551 ; free virtual = 44552 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 9529 ; free virtual = 44530 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9514 ; free virtual = 44515 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9539 ; free virtual = 44540 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 9545 ; free virtual = 44545 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9545 ; free virtual = 44546 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9555 ; free virtual = 44555 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9557 ; free virtual = 44558 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9559 ; free virtual = 44560 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9559 ; free virtual = 44559 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 7 Route finalize INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 63.961 ; free physical = 9532 ; free virtual = 44533 Phase 8 Verifying routed nets Verification completed successfully Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.465 ; gain = 66.961 ; free physical = 9530 ; free virtual = 44531 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.465 ; gain = 66.961 ; free physical = 9489 ; free virtual = 44490 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.465 ; gain = 66.961 ; free physical = 9526 ; free virtual = 44527 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.254 ; gain = 137.766 ; free physical = 9525 ; free virtual = 44526 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9496 ; free virtual = 44496 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9489 ; free virtual = 44490 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.398 ; gain = 501.531 ; free physical = 9469 ; free virtual = 44470 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9464 ; free virtual = 44466 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9461 ; free virtual = 44463 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9457 ; free virtual = 44461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2129.254 ; gain = 0.000 ; free physical = 9457 ; free virtual = 44461 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9457 ; free virtual = 44461 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.398 ; gain = 501.531 ; free physical = 9457 ; free virtual = 44461 --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9457 ; free virtual = 44461 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 9455 ; free virtual = 44459 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 9457 ; free virtual = 44461 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.398 ; gain = 501.531 ; free physical = 9434 ; free virtual = 44435 Phase 2 Final Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 501.531 ; free physical = 9359 ; free virtual = 44361 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9364 ; free virtual = 44366 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9365 ; free virtual = 44367 Loading route data... Processing options... Creating bitmap... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 501.531 ; free physical = 9276 ; free virtual = 44277 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 9278 ; free virtual = 44280 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:23:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2469.273 ; gain = 338.105 ; free physical = 9313 ; free virtual = 44314 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:23:06 2019... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 9376 ; free virtual = 44377 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28358 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28413 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 10043 ; free virtual = 45046 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 10013 ; free virtual = 45016 Loading data files... Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 10023 ; free virtual = 45026 Phase 2 Final Placement Cleanup Writing bitstream ./design.bit... Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 10013 ; free virtual = 45020 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 10184 ; free virtual = 45191 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 10277 ; free virtual = 45284 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:23:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2462.559 ; gain = 335.176 ; free physical = 9894 ; free virtual = 44901 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:23:15 2019... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28540 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 10603 ; free virtual = 45610 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Config size: 1060815 words Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 10592 ; free virtual = 45599 Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 10546 ; free virtual = 45553 Phase 1.3 Build Placer Netlist Model touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 10546 ; free virtual = 45554 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 10530 ; free virtual = 45538 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 10514 ; free virtual = 45521 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 10508 ; free virtual = 45515 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 10526 ; free virtual = 45533 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 10526 ; free virtual = 45533 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10494 ; free virtual = 45503 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 10494 ; free virtual = 45502 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10481 ; free virtual = 45490 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10480 ; free virtual = 45488 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10477 ; free virtual = 45486 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:55] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10274 ; free virtual = 45283 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10270 ; free virtual = 45279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10268 ; free virtual = 45277 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 10218 ; free virtual = 45227 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 9536 ; free virtual = 44545 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9523 ; free virtual = 44531 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9433 ; free virtual = 44441 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9431 ; free virtual = 44440 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9429 ; free virtual = 44438 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9429 ; free virtual = 44438 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9429 ; free virtual = 44438 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 9430 ; free virtual = 44439 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 9431 ; free virtual = 44440 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 9645 ; free virtual = 44658 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Starting Routing Task --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 9661 ; free virtual = 44674 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9657 ; free virtual = 44670 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 9626 ; free virtual = 44639 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 9582 ; free virtual = 44595 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 9581 ; free virtual = 44594 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9551 ; free virtual = 44564 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9550 ; free virtual = 44563 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9546 ; free virtual = 44562 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9545 ; free virtual = 44562 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9545 ; free virtual = 44561 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9544 ; free virtual = 44562 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9543 ; free virtual = 44561 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9543 ; free virtual = 44556 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 9548 ; free virtual = 44562 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 100878403 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9536 ; free virtual = 44549 Phase 3 Initial Routing No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9523 ; free virtual = 44536 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9521 ; free virtual = 44534 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9520 ; free virtual = 44533 Phase 4 Rip-up And Reroute | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9519 ; free virtual = 44532 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9519 ; free virtual = 44532 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9519 ; free virtual = 44532 Phase 6 Post Hold Fix | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9518 ; free virtual = 44532 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9515 ; free virtual = 44528 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9515 ; free virtual = 44528 Phase 9 Depositing Routes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9515 ; free virtual = 44528 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9515 ; free virtual = 44528 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.234 ; gain = 8.684 ; free physical = 9550 ; free virtual = 44563 Routing Is Done. INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2140.023 ; gain = 47.473 ; free physical = 9550 ; free virtual = 44563 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9551 ; free virtual = 44564 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... INFO: [Project 1-570] Preparing netlist for logic optimization 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 9589 ; free virtual = 44602 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:23:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2140.023 ; gain = 0.000 ; free physical = 9591 ; free virtual = 44607 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. ## proc putl {lst} { ## foreach line $lst {puts $line} ## } write_bitstream completed successfully ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2463.430 ; gain = 334.176 ; free physical = 9598 ; free virtual = 44613 # generate_top INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:23:30 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:16] Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10458 ; free virtual = 45471 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10460 ; free virtual = 45474 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10462 ; free virtual = 45476 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10462 ; free virtual = 45475 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10463 ; free virtual = 45477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10464 ; free virtual = 45477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10470 ; free virtual = 45484 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10497 ; free virtual = 45511 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 10499 ; free virtual = 45513 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10448 ; free virtual = 45462 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10466 ; free virtual = 45480 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 10465 ; free virtual = 45480 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28796 INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-570] Preparing netlist for logic optimization Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1553.855 ; gain = 0.000 ; free physical = 10344 ; free virtual = 45358 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1553.855 ; gain = 0.000 ; free physical = 10315 ; free virtual = 45329 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 10305 ; free virtual = 45319 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 10122 ; free virtual = 45136 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 10032 ; free virtual = 45046 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 10031 ; free virtual = 45046 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 9929 ; free virtual = 44943 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9812 ; free virtual = 44827 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cf4d1b03 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9807 ; free virtual = 44821 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9653 ; free virtual = 44667 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9666 ; free virtual = 44680 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: Launching helper process for spawning children vivado processes--------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: Helper process launched with PID 28914 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9619 ; free virtual = 44634 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 9578 ; free virtual = 44592 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9558 ; free virtual = 44572 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9556 ; free virtual = 44571 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9550 ; free virtual = 44564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9550 ; free virtual = 44564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9550 ; free virtual = 44564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9549 ; free virtual = 44563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9549 ; free virtual = 44563 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9548 ; free virtual = 44563 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9549 ; free virtual = 44564 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9509 ; free virtual = 44524 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9494 ; free virtual = 44509 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9494 ; free virtual = 44509 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9404 ; free virtual = 44419 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2137.082 ; gain = 52.668 ; free physical = 8998 ; free virtual = 44014 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 8984 ; free virtual = 44000 --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2147.070 ; gain = 62.656 ; free physical = 8923 ; free virtual = 43938 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2147.070 ; gain = 62.656 ; free physical = 8921 ; free virtual = 43936 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8781 ; free virtual = 43795 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8716 ; free virtual = 43731 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] Phase 4.1 Global Iteration 0 | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8692 ; free virtual = 43707 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1225] Phase 4 Rip-up And Reroute | Checksum: 17ae0cba6 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1282] Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8662 ; free virtual = 43677 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1308] Phase 5 Delay and Skew Optimization WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7717] Phase 5 Delay and Skew Optimization | Checksum: 17ae0cba6 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7800] Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8628 ; free virtual = 43642 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 6.1 Hold Fix Iter | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8600 ; free virtual = 43615 Phase 6 Post Hold Fix | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8570 ; free virtual = 43585 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8470 ; free virtual = 43485 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8472 ; free virtual = 43487 Phase 9 Depositing Routes WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] Phase 9 Depositing Routes | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8454 ; free virtual = 43469 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2183.500 ; gain = 99.086 ; free physical = 8502 ; free virtual = 43518 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:48 . Memory (MB): peak = 2222.289 ; gain = 169.891 ; free physical = 8509 ; free virtual = 43526 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8454 ; free virtual = 43470 --------------------------------------------------------------------------------- Writing placer database... Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8454 ; free virtual = 43473 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8453 ; free virtual = 43473 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8445 ; free virtual = 43465 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8340 ; free virtual = 43363 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8330 ; free virtual = 43353 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 8321 ; free virtual = 43345 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8294 ; free virtual = 43318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 8265 ; free virtual = 43290 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 8172 ; free virtual = 43199 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29016 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8161 ; free virtual = 43192 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8162 ; free virtual = 43193 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8163 ; free virtual = 43194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8169 ; free virtual = 43201 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8174 ; free virtual = 43206 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8175 ; free virtual = 43206 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8175 ; free virtual = 43206 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8176 ; free virtual = 43208 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 8188 ; free virtual = 43220 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 8129 ; free virtual = 43161 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 8126 ; free virtual = 43159 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 8123 ; free virtual = 43156 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 8123 ; free virtual = 43156 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 8122 ; free virtual = 43155 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 8122 ; free virtual = 43155 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 8123 ; free virtual = 43156 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 8123 ; free virtual = 43156 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.62 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 8103 ; free virtual = 43137 Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2137.070 ; gain = 52.668 ; free physical = 8097 ; free virtual = 43135 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.387 ; gain = 498.531 ; free physical = 8088 ; free virtual = 43128 Phase 1.3 Build Placer Netlist Model Writing XDEF routing. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 2.1 Fix Topology Constraints INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2222.289 ; gain = 0.000 ; free physical = 8339 ; free virtual = 43386 Phase 2.1 Fix Topology Constraints | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2147.059 ; gain = 62.656 ; free physical = 8341 ; free virtual = 43388 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2147.059 ; gain = 62.656 ; free physical = 8342 ; free virtual = 43390 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8153 ; free virtual = 43176 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8004 ; free virtual = 43026 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8028 ; free virtual = 43050 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4 Rip-up And Reroute | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8037 ; free virtual = 43060 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8035 ; free virtual = 43058 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8034 ; free virtual = 43056 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 6 Post Hold Fix | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8033 ; free virtual = 43055 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 8029 ; free virtual = 43052 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8022 ; free virtual = 43044 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8020 ; free virtual = 43043 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 7990 ; free virtual = 43013 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2182.363 ; gain = 97.961 ; free physical = 8029 ; free virtual = 43052 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:49 . Memory (MB): peak = 2221.152 ; gain = 168.766 ; free physical = 8020 ; free virtual = 43043 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f35ea853 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 8001 ; free virtual = 43023 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 8003 ; free virtual = 43025 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7997 ; free virtual = 43020 Phase 1 Placer Initialization | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7989 ; free virtual = 43013 Phase 2 Global Placement Writing placer database... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.926 ; gain = 44.668 ; free physical = 7952 ; free virtual = 42978 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 7921 ; free virtual = 42948 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 7922 ; free virtual = 42949 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:24:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2473.129 ; gain = 333.105 ; free physical = 7925 ; free virtual = 42953 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:24:02 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 7918 ; free virtual = 42946 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8849 ; free virtual = 43881 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8873 ; free virtual = 43906 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8872 ; free virtual = 43905 Phase 5 Delay and Skew Optimization Bitstream size: 4243411 bytes Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8871 ; free virtual = 43903 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8868 ; free virtual = 43901 Config size: 1060815 words Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8867 ; free virtual = 43900 Number of configuration frames: 9996 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 498.531 ; free physical = 8866 ; free virtual = 43899 Phase 1.4 Constrain Clocks/Macros DONE Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8852 ; free virtual = 43887 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 8852 ; free virtual = 43887 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 8845 ; free virtual = 43881 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 8881 ; free virtual = 43917 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2121.758 ; gain = 135.516 ; free physical = 8880 ; free virtual = 43916 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 498.531 ; free physical = 8865 ; free virtual = 43902 touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 498.531 ; free physical = 8848 ; free virtual = 43890 Phase 2 Final Placement Cleanup Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 8848 ; free virtual = 43889 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 498.531 ; free physical = 8809 ; free virtual = 43850 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 498.531 ; free physical = 8859 ; free virtual = 43902 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 8892 ; free virtual = 43936 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 8940 ; free virtual = 43990 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2221.152 ; gain = 0.000 ; free physical = 8930 ; free virtual = 43982 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 8927 ; free virtual = 43979 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8900 ; free virtual = 43952 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8888 ; free virtual = 43941 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 251526ef8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8869 ; free virtual = 43922 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22b2d4cc3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8896 ; free virtual = 43949 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f4e1ad28 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8886 ; free virtual = 43940 Phase 3.5 Small Shape Detail Placement Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 8884 ; free virtual = 43937 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8849 ; free virtual = 43904 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2221.152 ; gain = 0.000 ; free physical = 8868 ; free virtual = 43895 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.5 Small Shape Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8868 ; free virtual = 43895 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8867 ; free virtual = 43894 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8869 ; free virtual = 43896 Phase 3 Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8869 ; free virtual = 43896 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.1 Post Commit Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8874 ; free virtual = 43902 Phase 4.2 Post Placement Cleanup Starting Routing Task Phase 4.2 Post Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8873 ; free virtual = 43900 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8872 ; free virtual = 43899 Phase 4.4 Final Placement Cleanup INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 4.4 Final Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8869 ; free virtual = 43897 Starting Placer Task Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8866 ; free virtual = 43893 Ending Placer Task | Checksum: 16e2e720d Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 8876 ; free virtual = 43903 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2084.543 ; gain = 659.605 ; free physical = 8875 ; free virtual = 43902 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Phase 1.1 Placer Initialization Netlist Sorting Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.746 ; gain = 0.000 ; free physical = 8872 ; free virtual = 43899 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1483.746 ; gain = 0.000 ; free physical = 8866 ; free virtual = 43893 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8731 ; free virtual = 43758 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8731 ; free virtual = 43759 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8731 ; free virtual = 43759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8741 ; free virtual = 43768 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8747 ; free virtual = 43774 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8759 ; free virtual = 43787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8759 ; free virtual = 43787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8766 ; free virtual = 43793 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8780 ; free virtual = 43807 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 8781 ; free virtual = 43809 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 898ec903 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8546 ; free virtual = 43573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8571 ; free virtual = 43598 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8573 ; free virtual = 43601 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8586 ; free virtual = 43614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 8265 ; free virtual = 43293 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 8217 ; free virtual = 43245 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 8217 ; free virtual = 43245 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 102.711 ; free physical = 8129 ; free virtual = 43156 Phase 3 Initial Routing Loading data files... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8117 ; free virtual = 43145 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8109 ; free virtual = 43137 Phase 4 Rip-up And Reroute | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8109 ; free virtual = 43136 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8108 ; free virtual = 43136 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8108 ; free virtual = 43136 Phase 6 Post Hold Fix | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8108 ; free virtual = 43136 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8092 ; free virtual = 43120 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 8091 ; free virtual = 43118 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 8089 ; free virtual = 43117 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 8121 ; free virtual = 43148 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2109.766 ; gain = 177.516 ; free physical = 8121 ; free virtual = 43148 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 8102 ; free virtual = 43131 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1416.719 ; gain = 333.828 ; free physical = 7943 ; free virtual = 42970 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.750 ; gain = 0.000 ; free physical = 7791 ; free virtual = 42819 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1482.750 ; gain = 0.000 ; free physical = 7780 ; free virtual = 42808 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 7227 ; free virtual = 42255 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 7124 ; free virtual = 42152 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 7098 ; free virtual = 42126 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 7141 ; free virtual = 42169 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 7001 ; free virtual = 42029 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6994 ; free virtual = 42022 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6983 ; free virtual = 42011 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6982 ; free virtual = 42010 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6977 ; free virtual = 42005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6976 ; free virtual = 42004 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6973 ; free virtual = 42002 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6964 ; free virtual = 41992 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 6965 ; free virtual = 41994 INFO: [Project 1-571] Translating synthesized netlist Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 6866 ; free virtual = 41894 Phase 1.3 Build Placer Netlist Model INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 6470 ; free virtual = 41498 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 6413 ; free virtual = 41441 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 6374 ; free virtual = 41402 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 6376 ; free virtual = 41404 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 6100 ; free virtual = 41128 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 6099 ; free virtual = 41127 INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.234 ; gain = 0.000 ; free physical = 6077 ; free virtual = 41105 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 509.531 ; free physical = 6041 ; free virtual = 41069 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 509.531 ; free physical = 6040 ; free virtual = 41068 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 509.531 ; free physical = 6063 ; free virtual = 41091 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 509.531 ; free physical = 6061 ; free virtual = 41089 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 509.531 ; free physical = 6061 ; free virtual = 41089 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.277 ; gain = 509.531 ; free physical = 6063 ; free virtual = 41091 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1993.277 ; gain = 576.562 ; free physical = 6063 ; free virtual = 41091 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30713 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5954 ; free virtual = 40982 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5933 ; free virtual = 40961 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5797 ; free virtual = 40825 Phase 3.3 Area Swap Optimization Writing bitstream ./design.bit... Loading site data... Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5765 ; free virtual = 40796 Phase 3.4 Pipeline Register Optimization Loading site data... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5847 ; free virtual = 40878 Phase 3.5 Small Shape Detail Placement Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... Creating bitstream... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5924 ; free virtual = 40957 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5929 ; free virtual = 40961 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5928 ; free virtual = 40960 Creating bitstream... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5928 ; free virtual = 40960 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:24:38 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2461.863 ; gain = 340.105 ; free physical = 5939 ; free virtual = 40971 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:24:38 2019... Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5944 ; free virtual = 40976 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 5993 ; free virtual = 41025 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 6379 ; free virtual = 41411 Phase 4.4 Final Placement Cleanup Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 6916 ; free virtual = 41949 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 6908 ; free virtual = 41940 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 6940 ; free virtual = 41973 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.195 ; gain = 623.949 ; free physical = 6940 ; free virtual = 41973 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 Writing bitstream ./design.bit... Writing bitstream ./design.bit... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 6890 ; free virtual = 41930 --------------------------------------------------------------------------------- Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.238 ; gain = 0.000 ; free physical = 7118 ; free virtual = 42159 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 7122 ; free virtual = 42163 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 7117 ; free virtual = 42158 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 7113 ; free virtual = 42154 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 7115 ; free virtual = 42156 Phase 2 Final Placement Cleanup INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6389] Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 7110 ; free virtual = 42151 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6472] INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1994.281 ; gain = 511.531 ; free physical = 7109 ; free virtual = 42150 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 1994.281 ; gain = 577.562 ; free physical = 7109 ; free virtual = 42150 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 7107 ; free virtual = 42149 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 7113 ; free virtual = 42155 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 7113 ; free virtual = 42154 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 7092 ; free virtual = 42134 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:24:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Starting Routing Task 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 2454.371 ; gain = 344.605 ; free physical = 7099 ; free virtual = 42141 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:24:47 2019... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:24:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:49 . Memory (MB): peak = 2608.449 ; gain = 386.160 ; free physical = 7509 ; free virtual = 42550 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:24:47 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 1 Build RT Design | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2056.938 ; gain = 92.668 ; free physical = 9065 ; free virtual = 44106 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2062.926 ; gain = 98.656 ; free physical = 9032 ; free virtual = 44073 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2062.926 ; gain = 98.656 ; free physical = 9032 ; free virtual = 44073 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 106d813e1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 9051 ; free virtual = 44097 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 9018 ; free virtual = 44064 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 9015 ; free virtual = 44061 Phase 4 Rip-up And Reroute | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 9015 ; free virtual = 44061 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 9015 ; free virtual = 44061 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 9015 ; free virtual = 44061 Phase 6 Post Hold Fix | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 9014 ; free virtual = 44060 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 8983 ; free virtual = 44029 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 8982 ; free virtual = 44028 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 8981 ; free virtual = 44027 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 9010 ; free virtual = 44056 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2111.770 ; gain = 179.516 ; free physical = 9011 ; free virtual = 44058 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2111.770 ; gain = 0.000 ; free physical = 8992 ; free virtual = 44040 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 8897 ; free virtual = 43948 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8832 ; free virtual = 43883 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8838 ; free virtual = 43888 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8857 ; free virtual = 43908 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8834 ; free virtual = 43885 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8824 ; free virtual = 43875 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8811 ; free virtual = 43862 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 8810 ; free virtual = 43861 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:24:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:50 . Memory (MB): peak = 2608.312 ; gain = 387.160 ; free physical = 8726 ; free virtual = 43777 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:24:56 2019... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 8802 ; free virtual = 43851 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 9756 ; free virtual = 44806 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9765 ; free virtual = 44815 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Phase 1 Build RT Design | Checksum: 14c2f3401 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 9676 ; free virtual = 44727 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9660 ; free virtual = 44710 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9660 ; free virtual = 44711 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9659 ; free virtual = 44710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9659 ; free virtual = 44709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9659 ; free virtual = 44710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9659 ; free virtual = 44709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9658 ; free virtual = 44709 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 9657 ; free virtual = 44707 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 9659 ; free virtual = 44709 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14c2f3401 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 9661 ; free virtual = 44712 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14c2f3401 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 9660 ; free virtual = 44711 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9575 ; free virtual = 44626 Phase 3 Initial Routing Number of Nodes with overlaps = 0 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 3 Initial Routing | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9554 ; free virtual = 44605 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9553 ; free virtual = 44604 Phase 4 Rip-up And Reroute | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9552 ; free virtual = 44603 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9550 ; free virtual = 44601 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9551 ; free virtual = 44602 Phase 6 Post Hold Fix | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9550 ; free virtual = 44601 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9547 ; free virtual = 44598 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9545 ; free virtual = 44596 Phase 9 Depositing Routes Phase 1 Build RT Design | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 9534 ; free virtual = 44585 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 9497 ; free virtual = 44548 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 9497 ; free virtual = 44548 Phase 9 Depositing Routes | Checksum: 15a0a7f4a Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9485 ; free virtual = 44536 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9529 ; free virtual = 44580 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:57 . Memory (MB): peak = 2217.777 ; gain = 165.391 ; free physical = 9528 ; free virtual = 44579 Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 129e3aa92 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9422 ; free virtual = 44477 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9443 ; free virtual = 44499 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9421 ; free virtual = 44478 Phase 4 Rip-up And Reroute | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9418 ; free virtual = 44476 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9403 ; free virtual = 44461 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9401 ; free virtual = 44459 Phase 6 Post Hold Fix | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9398 ; free virtual = 44455 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9348 ; free virtual = 44407 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9347 ; free virtual = 44407 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9346 ; free virtual = 44406 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2102.230 ; gain = 17.688 ; free physical = 9383 ; free virtual = 44443 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2141.020 ; gain = 56.477 ; free physical = 9383 ; free virtual = 44443 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2141.020 ; gain = 0.000 ; free physical = 9426 ; free virtual = 44490 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31297 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.777 ; gain = 0.000 ; free physical = 9119 ; free virtual = 44198 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 9045 ; free virtual = 44127 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.777 ; gain = 0.000 ; free physical = 9024 ; free virtual = 44079 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command write_bitstream Starting Placer Task Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 8896 ; free virtual = 43951 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 8889 ; free virtual = 43943 Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31377 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31433 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 8720 ; free virtual = 43778 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8565 ; free virtual = 43624 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8567 ; free virtual = 43627 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8571 ; free virtual = 43630 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8568 ; free virtual = 43627 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:25:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2455.875 ; gain = 344.105 ; free physical = 8563 ; free virtual = 43622 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:25:17 2019... Bitstream size: 4243411 bytes INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 Loading data files... Loading site data... Phase 1 Build RT Design | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.961 ; gain = 42.668 ; free physical = 9250 ; free virtual = 44309 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Loading route data... Processing options... Creating bitmap... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2074.949 ; gain = 49.656 ; free physical = 9202 ; free virtual = 44261 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2074.949 ; gain = 49.656 ; free physical = 9202 ; free virtual = 44261 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.254 ; gain = 62.961 ; free physical = 9186 ; free virtual = 44245 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 9172 ; free virtual = 44231 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9161 ; free virtual = 44220 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9159 ; free virtual = 44218 Phase 4 Rip-up And Reroute | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9158 ; free virtual = 44218 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9158 ; free virtual = 44218 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9157 ; free virtual = 44216 Phase 6 Post Hold Fix | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9157 ; free virtual = 44216 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.254 ; gain = 64.961 ; free physical = 9141 ; free virtual = 44200 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.254 ; gain = 67.961 ; free physical = 9140 ; free virtual = 44199 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.254 ; gain = 67.961 ; free physical = 9104 ; free virtual = 44163 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.254 ; gain = 67.961 ; free physical = 9140 ; free virtual = 44199 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2132.043 ; gain = 138.766 ; free physical = 9138 ; free virtual = 44197 Writing placer database... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31541 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2132.043 ; gain = 0.000 ; free physical = 9077 ; free virtual = 44140 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 8966 ; free virtual = 44026 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 8999 ; free virtual = 44060 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 8995 ; free virtual = 44056 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 8991 ; free virtual = 44051 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 8833 ; free virtual = 43893 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2130.426 ; gain = 39.230 ; free physical = 8653 ; free virtual = 43714 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.414 ; gain = 44.219 ; free physical = 8633 ; free virtual = 43693 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2135.414 ; gain = 44.219 ; free physical = 8633 ; free virtual = 43693 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 8616 ; free virtual = 43676 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8616 ; free virtual = 43677 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 8581 ; free virtual = 43642 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8577 ; free virtual = 43637 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8579 ; free virtual = 43640 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8575 ; free virtual = 43636 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8575 ; free virtual = 43635 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8575 ; free virtual = 43635 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8575 ; free virtual = 43635 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8575 ; free virtual = 43635 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8526 ; free virtual = 43586 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8522 ; free virtual = 43582 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8502 ; free virtual = 43562 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.469 ; gain = 63.273 ; free physical = 8519 ; free virtual = 43579 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2193.258 ; gain = 102.062 ; free physical = 8514 ; free virtual = 43575 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8325 ; free virtual = 43390 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8322 ; free virtual = 43387 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8320 ; free virtual = 43385 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8319 ; free virtual = 43384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8317 ; free virtual = 43383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8318 ; free virtual = 43383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8315 ; free virtual = 43380 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8317 ; free virtual = 43383 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8317 ; free virtual = 43383 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 8287 ; free virtual = 43353 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading data files... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 8293 ; free virtual = 43361 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 8277 ; free virtual = 43346 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 8269 ; free virtual = 43338 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 8263 ; free virtual = 43332 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 8255 ; free virtual = 43324 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 8245 ; free virtual = 43314 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 8245 ; free virtual = 43313 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks Writing bitstream ./design.bit... INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Loading route data... Phase 1 Build RT Design | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.965 ; gain = 42.668 ; free physical = 8370 ; free virtual = 43454 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.953 ; gain = 48.656 ; free physical = 8332 ; free virtual = 43416 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.953 ; gain = 48.656 ; free physical = 8331 ; free virtual = 43415 Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 8304 ; free virtual = 43391 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 8265 ; free virtual = 43353 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2087.258 ; gain = 60.961 ; free physical = 8213 ; free virtual = 43301 Phase 3 Initial Routing INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 8204 ; free virtual = 43270 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8200 ; free virtual = 43266 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8193 ; free virtual = 43259 Phase 4 Rip-up And Reroute | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8182 ; free virtual = 43247 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8174 ; free virtual = 43240 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8171 ; free virtual = 43237 Phase 6 Post Hold Fix | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8166 ; free virtual = 43232 Phase 7 Route finalize Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 8156 ; free virtual = 43222 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.258 ; gain = 61.961 ; free physical = 8145 ; free virtual = 43211 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.258 ; gain = 64.961 ; free physical = 8135 ; free virtual = 43201 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8134 ; free virtual = 43200 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.258 ; gain = 65.961 ; free physical = 8048 ; free virtual = 43114 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.258 ; gain = 65.961 ; free physical = 8079 ; free virtual = 43144 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2131.047 ; gain = 136.766 ; free physical = 8078 ; free virtual = 43144 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:25:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2475.125 ; gain = 334.105 ; free physical = 8126 ; free virtual = 43192 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:25:33 2019... Writing placer database... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Writing XDEF routing. Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:63] Writing XDEF routing logical nets. Writing XDEF routing special nets. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2470] Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2131.047 ; gain = 0.000 ; free physical = 8194 ; free virtual = 43263 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. touch build/specimen_009/OK 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 9052 ; free virtual = 44120 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9066 ; free virtual = 44137 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9061 ; free virtual = 44135 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9057 ; free virtual = 44133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9057 ; free virtual = 44133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9054 ; free virtual = 44129 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9051 ; free virtual = 44128 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9051 ; free virtual = 44127 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9049 ; free virtual = 44125 Command: report_drc (run_mandatory_drcs) for: placer_checks Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 9049 ; free virtual = 44125 INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9009 ; free virtual = 44078 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9012 ; free virtual = 44080 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9010 ; free virtual = 44078 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9014 ; free virtual = 44082 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 9054 ; free virtual = 44122 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 9039 ; free virtual = 44106 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading data files... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 8372 ; free virtual = 43439 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Loading site data... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 8343 ; free virtual = 43411 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 8340 ; free virtual = 43407 Loading data files... Loading route data... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Processing options... Creating bitmap... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 8263 ; free virtual = 43331 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8262 ; free virtual = 43329 Phase 3 Initial Routing INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8259 ; free virtual = 43327 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8264 ; free virtual = 43332 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8264 ; free virtual = 43332 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8263 ; free virtual = 43331 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8263 ; free virtual = 43330 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8265 ; free virtual = 43333 Creating bitstream... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8250 ; free virtual = 43319 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 8242 ; free virtual = 43312 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 8218 ; free virtual = 43290 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 8255 ; free virtual = 43327 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 8254 ; free virtual = 43326 Writing placer database... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31814 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 8245 ; free virtual = 43328 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 8243 ; free virtual = 43327 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 8227 ; free virtual = 43318 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 8139 ; free virtual = 43209 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 8105 ; free virtual = 43195 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 8084 ; free virtual = 43154 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 8083 ; free virtual = 43153 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 8082 ; free virtual = 43152 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8071 ; free virtual = 43143 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8279 ; free virtual = 43353 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8279 ; free virtual = 43353 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8276 ; free virtual = 43350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8270 ; free virtual = 43344 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8269 ; free virtual = 43343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8269 ; free virtual = 43343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8264 ; free virtual = 43338 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8264 ; free virtual = 43338 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:28 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8262 ; free virtual = 43337 INFO: [Project 1-571] Translating synthesized netlist INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:25:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:46 . Memory (MB): peak = 2606.938 ; gain = 389.160 ; free physical = 7831 ; free virtual = 42905 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:25:52 2019... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 8834 ; free virtual = 43907 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... Loading site data... touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8651 ; free virtual = 43725 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:36 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 8898 ; free virtual = 43977 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] No constraint files found. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8918 ; free virtual = 43996 --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8861 ; free virtual = 43940 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8862 ; free virtual = 43941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 8895 ; free virtual = 43974 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8893 ; free virtual = 43972 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 8829 ; free virtual = 43907 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 8761 ; free virtual = 43839 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 8776 ; free virtual = 43855 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:25:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2470.148 ; gain = 338.105 ; free physical = 8704 ; free virtual = 43783 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:25:59 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9512 ; free virtual = 44592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 9477 ; free virtual = 44556 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 9470 ; free virtual = 44550 Phase 1.3 Build Placer Netlist Model Writing bitstream ./design.bit... Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 9465 ; free virtual = 44546 Phase 1.4 Constrain Clocks/Macros ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 9465 ; free virtual = 44546 ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 9462 ; free virtual = 44543 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 9460 ; free virtual = 44542 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 9457 ; free virtual = 44540 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 9457 ; free virtual = 44540 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9624 ; free virtual = 44708 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9607 ; free virtual = 44692 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9580 ; free virtual = 44664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9646 ; free virtual = 44730 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9644 ; free virtual = 44728 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9644 ; free virtual = 44728 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9644 ; free virtual = 44729 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9644 ; free virtual = 44729 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9646 ; free virtual = 44730 Loading site data... INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading route data... Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32086 Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:26:04 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2531.863 ; gain = 338.605 ; free physical = 9414 ; free virtual = 44498 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:26:04 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 10114 ; free virtual = 45198 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 10099 ; free virtual = 45187 Phase 1.3 Build Placer Netlist Model Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 10101 ; free virtual = 45185 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 10109 ; free virtual = 45193 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 10108 ; free virtual = 45193 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 10112 ; free virtual = 45197 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 10111 ; free virtual = 45196 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 10118 ; free virtual = 45203 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 10154 ; free virtual = 45239 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 10191 ; free virtual = 45278 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10188 ; free virtual = 45275 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10426 ; free virtual = 45516 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10426 ; free virtual = 45515 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10425 ; free virtual = 45514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10425 ; free virtual = 45514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10450 ; free virtual = 45540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10450 ; free virtual = 45540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10450 ; free virtual = 45539 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10449 ; free virtual = 45538 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 10450 ; free virtual = 45539 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:26:10 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2470.152 ; gain = 339.105 ; free physical = 10505 ; free virtual = 45598 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:26:10 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:26:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 11373 ; free virtual = 46466 --------------------------------------------------------------------------------- 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2471.363 ; gain = 343.105 ; free physical = 11375 ; free virtual = 46469 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:26:11 2019... touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 12197 ; free virtual = 47291 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Config size: 1060815 words Number of configuration frames: 9996 DONE Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 12284 ; free virtual = 47379 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 12284 ; free virtual = 47379 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 12305 ; free virtual = 47400 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 12276 ; free virtual = 47371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 12275 ; free virtual = 47370 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 12212 ; free virtual = 47308 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.227 ; gain = 0.000 ; free physical = 11711 ; free virtual = 46806 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 15c4992dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.957 ; gain = 43.668 ; free physical = 11628 ; free virtual = 46724 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 11629 ; free virtual = 46725 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 11629 ; free virtual = 46724 Phase 1.4 Constrain Clocks/Macros Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15c4992dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 11628 ; free virtual = 46723 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15c4992dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 11600 ; free virtual = 46696 Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 11597 ; free virtual = 46693 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 11577 ; free virtual = 46672 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 11563 ; free virtual = 46658 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 11563 ; free virtual = 46659 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 576.562 ; free physical = 11563 ; free virtual = 46659 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32427 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 11477 ; free virtual = 46573 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11461 ; free virtual = 46557 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11486 ; free virtual = 46582 Phase 4 Rip-up And Reroute | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11486 ; free virtual = 46581 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11486 ; free virtual = 46581 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11485 ; free virtual = 46581 Phase 6 Post Hold Fix | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11485 ; free virtual = 46580 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 11476 ; free virtual = 46571 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 11474 ; free virtual = 46570 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 11472 ; free virtual = 46567 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 11509 ; free virtual = 46604 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2131.164 ; gain = 136.891 ; free physical = 11509 ; free virtual = 46604 Writing placer database... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing XDEF routing. Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 1 Build RT Design Write XDEF Complete: Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2131.164 ; gain = 0.000 ; free physical = 11491 ; free virtual = 46590 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 11399 ; free virtual = 46496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 11367 ; free virtual = 46463 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11347 ; free virtual = 46443 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32491 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11288 ; free virtual = 46384 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11288 ; free virtual = 46384 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11287 ; free virtual = 46383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11287 ; free virtual = 46383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11287 ; free virtual = 46383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11287 ; free virtual = 46383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11286 ; free virtual = 46382 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11289 ; free virtual = 46386 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 11293 ; free virtual = 46389 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 11272 ; free virtual = 46368 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Loading data files... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1560.855 ; gain = 0.000 ; free physical = 10995 ; free virtual = 46091 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1560.855 ; gain = 0.000 ; free physical = 10983 ; free virtual = 46079 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32562 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 10752 ; free virtual = 45849 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 10606 ; free virtual = 45702 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10536 ; free virtual = 45633 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10506 ; free virtual = 45602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10505 ; free virtual = 45602 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 10470 ; free virtual = 45566 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10454 ; free virtual = 45551 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: eeeca7b0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10449 ; free virtual = 45546 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10181 ; free virtual = 45278 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 10105 ; free virtual = 45201 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9993 ; free virtual = 45090 Phase 1.3 Build Placer Netlist Model INFO: Helper process launched with PID 32645 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9989 ; free virtual = 45086 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9989 ; free virtual = 45086 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9989 ; free virtual = 45086 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9985 ; free virtual = 45082 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9984 ; free virtual = 45081 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 9984 ; free virtual = 45081 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32689 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9954 ; free virtual = 45052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9971 ; free virtual = 45069 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9970 ; free virtual = 45067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9954 ; free virtual = 45052 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 9706 ; free virtual = 44803 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9510 ; free virtual = 44607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9502 ; free virtual = 44599 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9498 ; free virtual = 44595 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9449 ; free virtual = 44546 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9446 ; free virtual = 44543 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9446 ; free virtual = 44543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9446 ; free virtual = 44543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9446 ; free virtual = 44543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9445 ; free virtual = 44542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9445 ; free virtual = 44542 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9445 ; free virtual = 44542 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 9447 ; free virtual = 44544 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:16] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9332 ; free virtual = 44430 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2063.922 ; gain = 45.668 ; free physical = 9328 ; free virtual = 44426 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.910 ; gain = 50.656 ; free physical = 9245 ; free virtual = 44346 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.910 ; gain = 50.656 ; free physical = 9244 ; free virtual = 44345 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9237 ; free virtual = 44339 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9252 ; free virtual = 44350 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9240 ; free virtual = 44338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 9227 ; free virtual = 44330 Phase 3 Initial Routing Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9203 ; free virtual = 44307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9170 ; free virtual = 44267 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 9166 ; free virtual = 44264 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9193 ; free virtual = 44291 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9191 ; free virtual = 44289 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9189 ; free virtual = 44287 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9188 ; free virtual = 44286 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9188 ; free virtual = 44286 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9185 ; free virtual = 44283 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 9156 ; free virtual = 44254 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 9152 ; free virtual = 44250 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 9136 ; free virtual = 44233 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 9170 ; free virtual = 44268 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2121.754 ; gain = 135.516 ; free physical = 9170 ; free virtual = 44268 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9058 ; free virtual = 44155 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9046 ; free virtual = 44145 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Writing XDEF routing. --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9041 ; free virtual = 44140 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9038 ; free virtual = 44138 --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9038 ; free virtual = 44137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9037 ; free virtual = 44137 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9036 ; free virtual = 44135 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2121.754 ; gain = 0.000 ; free physical = 9028 ; free virtual = 44128 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9023 ; free virtual = 44123 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 9018 ; free virtual = 44119 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 8996 ; free virtual = 44096 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8784 ; free virtual = 43883 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8791 ; free virtual = 43890 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8790 ; free virtual = 43889 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8780 ; free virtual = 43879 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 8803 ; free virtual = 43901 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:251] Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 8784 ; free virtual = 43883 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1371] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2323] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:16] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 8766 ; free virtual = 43865 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:7] Writing bitstream ./design.bit... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8790 ; free virtual = 43892 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8889 ; free virtual = 43992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8895 ; free virtual = 43998 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 9042 ; free virtual = 44145 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9025 ; free virtual = 44128 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14eeb77a5 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9023 ; free virtual = 44125 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 8910 ; free virtual = 44013 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2062.930 ; gain = 43.668 ; free physical = 8703 ; free virtual = 43805 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.918 ; gain = 49.656 ; free physical = 8634 ; free virtual = 43737 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.918 ; gain = 49.656 ; free physical = 8632 ; free virtual = 43735 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.973 ; gain = 59.711 ; free physical = 8449 ; free virtual = 43552 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. Loading data files... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8375 ; free virtual = 43477 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8374 ; free virtual = 43477 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8374 ; free virtual = 43476 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8373 ; free virtual = 43476 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8373 ; free virtual = 43476 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8373 ; free virtual = 43476 Phase 7 Route finalize INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1909.457 ; gain = 0.000 ; free physical = 8375 ; free virtual = 43477 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 8398 ; free virtual = 43501 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 8396 ; free virtual = 43499 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 8396 ; free virtual = 43499 Phase 9 Depositing Routes INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 8390 ; free virtual = 43493 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 8425 ; free virtual = 43528 Routing Is Done. Command: report_drc (run_mandatory_drcs) for: placer_checks 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully INFO: [DRC 23-27] Running DRC with 8 threads route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2121.762 ; gain = 134.516 ; free physical = 8425 ; free virtual = 43528 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 8390 ; free virtual = 43496 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b1503975 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 8303 ; free virtual = 43408 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 248a29f5b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 8296 ; free virtual = 43404 Phase 1.4 Constrain Clocks/Macros Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 248a29f5b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 8294 ; free virtual = 43397 Phase 1 Placer Initialization | Checksum: 248a29f5b Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 8291 ; free virtual = 43394 Phase 2 Global Placement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8230 ; free virtual = 43334 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8234 ; free virtual = 43337 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8245 ; free virtual = 43349 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:26:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8223 ; free virtual = 43326 --------------------------------------------------------------------------------- 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.270 ; gain = 339.105 ; free physical = 8222 ; free virtual = 43326 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:26:54 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 8237 ; free virtual = 43340 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 8788 ; free virtual = 43891 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 9137 ; free virtual = 44241 Phase 2 Final Placement Cleanup DONE --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9140 ; free virtual = 44244 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 9123 ; free virtual = 44227 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 491.531 ; free physical = 9138 ; free virtual = 44242 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 9136 ; free virtual = 44240 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9045 ; free virtual = 44150 --------------------------------------------------------------------------------- No constraint files found. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9023 ; free virtual = 44128 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9022 ; free virtual = 44126 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8997 ; free virtual = 44102 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8993 ; free virtual = 44098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 8988 ; free virtual = 44093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8988 ; free virtual = 44092 | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8985 ; free virtual = 44090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8985 ; free virtual = 44089 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8981 ; free virtual = 44085 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 8979 ; free virtual = 44084 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8971 ; free virtual = 44076 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8922 ; free virtual = 44027 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8934 ; free virtual = 44039 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2559e6f74 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8942 ; free virtual = 44047 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22f794d3f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8991 ; free virtual = 44097 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f92dada4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 9000 ; free virtual = 44107 Phase 3.5 Small Shape Detail Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8996 ; free virtual = 44102 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8980 ; free virtual = 44086 Phase 3.7 Pipeline Register Optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 8976 ; free virtual = 44082 --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8974 ; free virtual = 44080 Phase 3 Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8967 ; free virtual = 44073 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8972 ; free virtual = 44078 Phase 4.2 Post Placement Cleanup report_drc (run_mandatory_drcs) completed successfully Phase 4.2 Post Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8988 ; free virtual = 44093 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8986 ; free virtual = 44091 Starting Routing Task Phase 4.4 Final Placement Cleanup INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 4.4 Final Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8965 ; free virtual = 44071 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8963 ; free virtual = 44069 Ending Placer Task | Checksum: fb45469f Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2093.547 ; gain = 604.578 ; free physical = 8976 ; free virtual = 44082 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.547 ; gain = 668.609 ; free physical = 8985 ; free virtual = 44090 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 8980 ; free virtual = 44085 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8979 ; free virtual = 44085 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8975 ; free virtual = 44081 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8964 ; free virtual = 44070 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8956 ; free virtual = 44061 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8968 ; free virtual = 44074 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8967 ; free virtual = 44073 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: Phase 1 Build RT Design +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8965 ; free virtual = 44071 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8961 ; free virtual = 44067 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 8962 ; free virtual = 44068 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8953 ; free virtual = 44059 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8895 ; free virtual = 44001 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8895 ; free virtual = 44001 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8893 ; free virtual = 43999 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8893 ; free virtual = 43999 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8893 ; free virtual = 43999 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading data files... Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8893 ; free virtual = 43999 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8893 ; free virtual = 43999 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 8893 ; free virtual = 43998 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8894 ; free virtual = 44000 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 16a59d95 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 18a962264 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.953 ; gain = 42.668 ; free physical = 8356 ; free virtual = 43462 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18a962264 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.941 ; gain = 48.656 ; free physical = 8314 ; free virtual = 43419 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18a962264 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.941 ; gain = 48.656 ; free physical = 8312 ; free virtual = 43418 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 8305 ; free virtual = 43410 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.246 ; gain = 60.961 ; free physical = 8257 ; free virtual = 43362 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8240 ; free virtual = 43346 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8239 ; free virtual = 43345 Phase 4 Rip-up And Reroute | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8239 ; free virtual = 43345 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8238 ; free virtual = 43344 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8236 ; free virtual = 43342 Phase 6 Post Hold Fix | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8234 ; free virtual = 43340 Phase 7 Route finalize INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 8253 ; free virtual = 43359 Phase 7 Route finalize | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.246 ; gain = 63.961 ; free physical = 8253 ; free virtual = 43359 Phase 8 Verifying routed nets Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Verification completed successfully INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 8 Verifying routed nets | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.246 ; gain = 65.961 ; free physical = 8251 ; free virtual = 43357 Phase 9 Depositing Routes INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8251 ; free virtual = 43357 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8221 ; free virtual = 43327 Phase 9 Depositing Routes | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.246 ; gain = 65.961 ; free physical = 8215 ; free virtual = 43321 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.246 ; gain = 65.961 ; free physical = 8249 ; free virtual = 43355 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.035 ; gain = 136.766 ; free physical = 8248 ; free virtual = 43353 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:01 . Memory (MB): peak = 2130.035 ; gain = 0.000 ; free physical = 8136 ; free virtual = 43245 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8101 ; free virtual = 43210 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 165c53615 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8090 ; free virtual = 43199 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 7915 ; free virtual = 43022 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 7631 ; free virtual = 42738 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 7571 ; free virtual = 42677 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 104554cdc Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7503 ; free virtual = 42610 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7450 ; free virtual = 42556 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7457 ; free virtual = 42563 Loading site data... Phase 1 Placer Initialization | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 7468 ; free virtual = 42574 Phase 2 Global Placement Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.61 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 7461 ; free virtual = 42568 Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... Phase 2 Global Placement | Checksum: 19390bb85 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7613 ; free virtual = 42724 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19390bb85 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7609 ; free virtual = 42719 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22760be29 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7605 ; free virtual = 42715 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2013b9bf4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7589 ; free virtual = 42700 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1caeffc59 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7587 ; free virtual = 42698 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7469 ; free virtual = 42580 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7453 ; free virtual = 42564 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7441 ; free virtual = 42551 Phase 3 Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7418 ; free virtual = 42528 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7391 ; free virtual = 42501 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7363 ; free virtual = 42474 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7347 ; free virtual = 42457 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7332 ; free virtual = 42443 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7340 ; free virtual = 42450 Ending Placer Task | Checksum: 1d105b369 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 7353 ; free virtual = 42464 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 7353 ; free virtual = 42463 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 7242 ; free virtual = 42358 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:27:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2460.859 ; gain = 339.105 ; free physical = 7242 ; free virtual = 42359 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:27:19 2019... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 7285 ; free virtual = 42402 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 7340 ; free virtual = 42456 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 7378 ; free virtual = 42495 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 7989 ; free virtual = 43106 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8216 ; free virtual = 43332 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Creating bitstream... Bitstream size: 4243411 bytes Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8216 ; free virtual = 43333 Config size: 1060815 words 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 8215 ; free virtual = 43331 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of configuration frames: 9996 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' DONE Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec660a5f ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2245 Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 147c14821 Time (s): cpu = 00:00:39 ; elapsed = 00:00:47 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 8201 ; free virtual = 43317 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8273 ; free virtual = 43388 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8274 ; free virtual = 43389 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8288 ; free virtual = 43404 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8235 ; free virtual = 43351 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8230 ; free virtual = 43347 Phase 4 Rip-up And Reroute | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8230 ; free virtual = 43346 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8229 ; free virtual = 43345 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8229 ; free virtual = 43345 Phase 6 Post Hold Fix | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8229 ; free virtual = 43345 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8239 ; free virtual = 43355 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 8237 ; free virtual = 43353 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 8237 ; free virtual = 43353 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 8270 ; free virtual = 43386 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 8269 ; free virtual = 43385 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 8267 ; free virtual = 43385 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:27:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2460.867 ; gain = 339.105 ; free physical = 8117 ; free virtual = 43233 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:27:26 2019... Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 8474 ; free virtual = 43590 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8337 ; free virtual = 43453 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8270 ; free virtual = 43386 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8236 ; free virtual = 43353 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8207 ; free virtual = 43324 Phase 2 Final Placement Cleanup Loading data files... Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8197 ; free virtual = 43314 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 8187 ; free virtual = 43304 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 8185 ; free virtual = 43302 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1909.453 ; gain = 0.000 ; free physical = 8137 ; free virtual = 43254 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e0a71f46 Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 8037 ; free virtual = 43153 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 277f9852c Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 8034 ; free virtual = 43151 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 277f9852c Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 8033 ; free virtual = 43149 Phase 1 Placer Initialization | Checksum: 277f9852c Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 8035 ; free virtual = 43152 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 7744 ; free virtual = 42860 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 7702 ; free virtual = 42819 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Global Placement | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7587 ; free virtual = 42703 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7663 ; free virtual = 42779 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2433660c9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7655 ; free virtual = 42772 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d113e94 Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7657 ; free virtual = 42774 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6c59ef9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7657 ; free virtual = 42774 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 7654 ; free virtual = 42771 Phase 1.3 Build Placer Netlist Model Phase 3.5 Small Shape Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7635 ; free virtual = 42752 Phase 3.6 Re-assign LUT pins Writing bitstream ./design.bit... Phase 3.6 Re-assign LUT pins | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7635 ; free virtual = 42752 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7635 ; free virtual = 42753 Phase 3 Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7634 ; free virtual = 42752 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7633 ; free virtual = 42752 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7632 ; free virtual = 42752 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7632 ; free virtual = 42752 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7632 ; free virtual = 42753 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7642 ; free virtual = 42762 Ending Placer Task | Checksum: 1d0f627a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2085.539 ; gain = 596.574 ; free physical = 7684 ; free virtual = 42804 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 2085.539 ; gain = 660.605 ; free physical = 7685 ; free virtual = 42805 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec567e97 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 7814 ; free virtual = 42938 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 7769 ; free virtual = 42897 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 7772 ; free virtual = 42893 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 7779 ; free virtual = 42900 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 7698 ; free virtual = 42819 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 7697 ; free virtual = 42818 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:27:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2470.141 ; gain = 340.105 ; free physical = 7691 ; free virtual = 42813 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:27:42 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 8505 ; free virtual = 43628 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8477 ; free virtual = 43600 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3894 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Phase 1 Build RT Design | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2093.547 ; gain = 0.000 ; free physical = 8480 ; free virtual = 43603 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8480 ; free virtual = 43603 Phase 3.2 Commit Most Macros & LUTRAMs Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2093.547 ; gain = 0.000 ; free physical = 8462 ; free virtual = 43585 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2093.547 ; gain = 0.000 ; free physical = 8461 ; free virtual = 43584 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8418 ; free virtual = 43541 Phase 3.3 Area Swap Optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174587064 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8405 ; free virtual = 43529 Phase 3 Initial Routing Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8398 ; free virtual = 43522 Phase 3.4 Pipeline Register Optimization Phase 1 Build RT Design | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 8396 ; free virtual = 43520 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8392 ; free virtual = 43515 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8391 ; free virtual = 43514 Phase 4 Rip-up And Reroute | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8391 ; free virtual = 43514 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8390 ; free virtual = 43514 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8390 ; free virtual = 43514 Phase 3.5 Small Shape Detail Placement Phase 6.1 Hold Fix Iter | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8390 ; free virtual = 43514 Phase 6 Post Hold Fix | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8390 ; free virtual = 43514 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8336 ; free virtual = 43459 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8336 ; free virtual = 43459 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8331 ; free virtual = 43454 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.230 ; gain = 8.684 ; free physical = 8367 ; free virtual = 43490 Routing Is Done. Phase 2.1 Fix Topology Constraints | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 8367 ; free virtual = 43490 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully Phase 2.2 Pre Route Cleanup route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2141.020 ; gain = 47.473 ; free physical = 8367 ; free virtual = 43490 Writing bitstream ./design.bit... Phase 2.2 Pre Route Cleanup | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 8358 ; free virtual = 43482 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2141.020 ; gain = 0.000 ; free physical = 8343 ; free virtual = 43472 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8520 ; free virtual = 43648 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8560 ; free virtual = 43687 Phase 3.6 Re-assign LUT pins Phase 3 Initial Routing | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8559 ; free virtual = 43687 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8548 ; free virtual = 43676 Phase 4 Rip-up And Reroute | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8548 ; free virtual = 43675 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8547 ; free virtual = 43675 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8548 ; free virtual = 43676 Phase 3.7 Pipeline Register Optimization Phase 6.1 Hold Fix Iter | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8544 ; free virtual = 43672 Phase 6 Post Hold Fix | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8539 ; free virtual = 43666 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8529 ; free virtual = 43657 Phase 8 Verifying routed nets Verification completed successfully Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8525 ; free virtual = 43653 Phase 8 Verifying routed nets | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8524 ; free virtual = 43652 Phase 9 Depositing Routes Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8502 ; free virtual = 43629 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 9 Depositing Routes | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8503 ; free virtual = 43631 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2181.488 ; gain = 97.086 ; free physical = 8546 ; free virtual = 43674 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2220.277 ; gain = 167.891 ; free physical = 8546 ; free virtual = 43674 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8546 ; free virtual = 43674 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8525 ; free virtual = 43653 Phase 4.3 Placer Reporting Writing placer database... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8515 ; free virtual = 43646 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8513 ; free virtual = 43645 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8507 ; free virtual = 43644 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:27:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8551 ; free virtual = 43686 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.199 ; gain = 623.949 ; free physical = 8551 ; free virtual = 43685 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 8555 ; free virtual = 43690 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:27:51 2019... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8778 ; free virtual = 43915 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9458 ; free virtual = 44597 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9388 ; free virtual = 44531 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing XDEF routing. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9278 ; free virtual = 44430 --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9276 ; free virtual = 44429 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2220.277 ; gain = 0.000 ; free physical = 9268 ; free virtual = 44424 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9260 ; free virtual = 44416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9244 ; free virtual = 44400 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9234 ; free virtual = 44390 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9243 ; free virtual = 44399 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9254 ; free virtual = 44410 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9252 ; free virtual = 44408 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9253 ; free virtual = 44409 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4143 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 9147 ; free virtual = 44278 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 8987 ; free virtual = 44118 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9011 ; free virtual = 44143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9009 ; free virtual = 44140 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 8984 ; free virtual = 44115 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading site data... Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 8391 ; free virtual = 43523 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 8339 ; free virtual = 43470 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 8338 ; free virtual = 43470 Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 8340 ; free virtual = 43471 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 8377 ; free virtual = 43509 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 171fe028c Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8342 ; free virtual = 43474 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8259 ; free virtual = 43390 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8242 ; free virtual = 43373 Phase 4 Rip-up And Reroute | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8237 ; free virtual = 43368 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8235 ; free virtual = 43367 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8235 ; free virtual = 43367 Phase 6 Post Hold Fix | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8233 ; free virtual = 43364 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Congestion Report Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 North Dir Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1x1 Area, Max Cong = 3.6036 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 %, No Congested Regions. Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 South Dir 1x1 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Area, Max Cong = 1.8018%, Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 No Congested Regions. Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 East Dir Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1x1 Area, Max Cong = 2.94118 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 %, No Congested Regions. Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 West Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Dir 1x1 Area, Max Cong = Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 8.82353%, No Congested Regions. Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] Phase 7 Route finalize | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8248 ; free virtual = 43379 Phase 8 Verifying routed nets Verification completed successfully WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] Phase 8 Verifying routed nets | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8247 ; free virtual = 43379 Phase 9 Depositing Routes WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] Phase 9 Depositing Routes | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8232 ; free virtual = 43364 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 8264 ; free virtual = 43396 Routing Is Done. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 8256 ; free virtual = 43387 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 8235 ; free virtual = 43373 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 8272 ; free virtual = 43407 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 8306 ; free virtual = 43438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 8301 ; free virtual = 43433 --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 8269 ; free virtual = 43401 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 8227 ; free virtual = 43359 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } Phase 1 Build RT Design | Checksum: f9126c41 ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 8185 ; free virtual = 43317 ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 8143 ; free virtual = 43275 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 8141 ; free virtual = 43273 Loading data files... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.60 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 8121 ; free virtual = 43253 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 8166 ; free virtual = 43298 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8107 ; free virtual = 43239 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8077 ; free virtual = 43209 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 8075 ; free virtual = 43208 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8069 ; free virtual = 43201 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8070 ; free virtual = 43203 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8068 ; free virtual = 43200 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8058 ; free virtual = 43191 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8065 ; free virtual = 43197 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8065 ; free virtual = 43198 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 8049 ; free virtual = 43182 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 8049 ; free virtual = 43181 Phase 9 Depositing Routes INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.469 ; gain = 66.961 ; free physical = 8040 ; free virtual = 43172 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.469 ; gain = 66.961 ; free physical = 8077 ; free virtual = 43209 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2129.258 ; gain = 137.766 ; free physical = 8076 ; free virtual = 43209 Writing placer database... Writing XDEF routing. INFO: Launching helper process for spawning children vivado processes Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: Helper process launched with PID 4276 Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2129.258 ; gain = 0.000 ; free physical = 8046 ; free virtual = 43182 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit --------------------------------------------------------------------------------- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8048 ; free virtual = 43181 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8046 ; free virtual = 43178 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8043 ; free virtual = 43176 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8042 ; free virtual = 43175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8042 ; free virtual = 43174 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8041 ; free virtual = 43174 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8037 ; free virtual = 43170 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 8034 ; free virtual = 43166 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8035 ; free virtual = 43168 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.480 ; free physical = 7730 ; free virtual = 42867 --------------------------------------------------------------------------------- Loading data files... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 7705 ; free virtual = 42842 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.480 ; free physical = 7705 ; free virtual = 42842 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 7660 ; free virtual = 42798 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2072.164 ; gain = 48.656 ; free physical = 7667 ; free virtual = 42804 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7665 ; free virtual = 42802 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4352 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.469 ; gain = 59.961 ; free physical = 7606 ; free virtual = 42743 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7554 ; free virtual = 42691 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7550 ; free virtual = 42687 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7550 ; free virtual = 42687 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7550 ; free virtual = 42687 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7549 ; free virtual = 42686 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7548 ; free virtual = 42685 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7547 ; free virtual = 42684 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7549 ; free virtual = 42686 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7549 ; free virtual = 42686 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7549 ; free virtual = 42686 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7550 ; free virtual = 42687 --------------------------------------------------------------------------------- Phase 7 Route finalize --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7549 ; free virtual = 42686 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7550 ; free virtual = 42687 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 7553 ; free virtual = 42690 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.914 ; gain = 218.457 ; free physical = 7556 ; free virtual = 42694 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 7525 ; free virtual = 42662 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 7531 ; free virtual = 42668 Phase 9 Depositing Routes 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 7549 ; free virtual = 42686 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 7544 ; free virtual = 42681 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 7581 ; free virtual = 42718 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 7580 ; free virtual = 42717 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.50 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 7454 ; free virtual = 42595 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:28:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2474.125 ; gain = 333.105 ; free physical = 7372 ; free virtual = 42509 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:28:19 2019... Loading route data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Processing options... Creating bitmap... Starting Placer Task INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 7681 ; free virtual = 42818 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 8363 ; free virtual = 43501 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Running DRC as a precondition to command write_bitstream DONE Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.434 ; gain = 55.992 ; free physical = 8344 ; free virtual = 43482 --------------------------------------------------------------------------------- touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2968] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3798] INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 8024 ; free virtual = 43163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 8000 ; free virtual = 43139 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 7999 ; free virtual = 43138 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 7895 ; free virtual = 43034 --------------------------------------------------------------------------------- 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1404.930 ; gain = 322.039 ; free physical = 7896 ; free virtual = 43035 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 10fbb77b1 INFO: [DRC 23-27] Running DRC with 8 threads Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.539 ; gain = 0.000 ; free physical = 7894 ; free virtual = 43033 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.539 ; gain = 0.000 ; free physical = 7852 ; free virtual = 42991 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10fbb77b1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.539 ; gain = 0.000 ; free physical = 7852 ; free virtual = 42991 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174384e93 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7778 ; free virtual = 42917 Phase 3 Initial Routing Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 7778 ; free virtual = 42917 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 7765 ; free virtual = 42904 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7743 ; free virtual = 42882 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7737 ; free virtual = 42876 Phase 4 Rip-up And Reroute | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7738 ; free virtual = 42877 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7738 ; free virtual = 42877 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7736 ; free virtual = 42875 Phase 6 Post Hold Fix | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7733 ; free virtual = 42872 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7719 ; free virtual = 42858 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7715 ; free virtual = 42854 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 706f0e10 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7708 ; free virtual = 42847 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2101.227 ; gain = 15.688 ; free physical = 7744 ; free virtual = 42883 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2140.016 ; gain = 54.477 ; free physical = 7743 ; free virtual = 42882 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 7680 ; free virtual = 42821 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:14 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 7268 ; free virtual = 42407 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 7244 ; free virtual = 42383 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 7130 ; free virtual = 42269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 7140 ; free virtual = 42280 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 7139 ; free virtual = 42279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 7174 ; free virtual = 42314 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Device 21-403] Loading part xc7z020clg400-1 Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7149 ; free virtual = 42289 Phase 1.3 Build Placer Netlist Model Creating bitstream... Writing bitstream ./design.bit... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.680 ; gain = 215.238 ; free physical = 7327 ; free virtual = 42471 --------------------------------------------------------------------------------- INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.680 ; gain = 215.238 ; free physical = 7258 ; free virtual = 42401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7263 ; free virtual = 42407 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... Writing bitstream ./design.bit... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7263 ; free virtual = 42413 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7271 ; free virtual = 42421 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7281 ; free virtual = 42431 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7285 ; free virtual = 42435 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7289 ; free virtual = 42439 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7290 ; free virtual = 42441 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7291 ; free virtual = 42442 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 7296 ; free virtual = 42447 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 7299 ; free virtual = 42451 INFO: [Project 1-571] Translating synthesized netlist Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7437 ; free virtual = 42588 Phase 1.4 Constrain Clocks/Macros INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7751 ; free virtual = 42903 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7756 ; free virtual = 42907 Phase 2 Global Placement Loading site data... Loading route data... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Processing options... Creating bitmap... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:28:38 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:44 . Memory (MB): peak = 2608.438 ; gain = 388.160 ; free physical = 7618 ; free virtual = 42770 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:28:38 2019... INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2130.633 ; gain = 39.434 ; free physical = 8567 ; free virtual = 43718 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.621 ; gain = 45.422 ; free physical = 8583 ; free virtual = 43734 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.621 ; gain = 45.422 ; free physical = 8582 ; free virtual = 43734 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:28:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2470.363 ; gain = 341.105 ; free physical = 8564 ; free virtual = 43715 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:28:40 2019... touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 8674 ; free virtual = 43826 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 8909 ; free virtual = 44061 Phase 3 Initial Routing Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 9490 ; free virtual = 44642 Phase 3.2 Commit Most Macros & LUTRAMs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9455 ; free virtual = 44606 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9448 ; free virtual = 44600 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9448 ; free virtual = 44600 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9448 ; free virtual = 44600 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9448 ; free virtual = 44599 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9447 ; free virtual = 44599 touch build/specimen_011/OK INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:28:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 Phase 7 Route finalize 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2474.125 ; gain = 334.105 ; free physical = 9458 ; free virtual = 44610 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:28:40 2019... Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9472 ; free virtual = 44624 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9475 ; free virtual = 44627 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9487 ; free virtual = 44639 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.676 ; gain = 64.477 ; free physical = 9534 ; free virtual = 44686 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:50 . Memory (MB): peak = 2194.465 ; gain = 103.266 ; free physical = 9537 ; free virtual = 44689 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 9547 ; free virtual = 44699 Creating bitstream... Phase 3.3 Area Swap Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 3.3 Area Swap Optimization | Checksum: 23216312d DONE Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10410 ; free virtual = 45569 Phase 3.4 Pipeline Register Optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 10428 ; free virtual = 45588 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10397 ; free virtual = 45558 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 10395 ; free virtual = 45556 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10382 ; free virtual = 45543 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10114 ; free virtual = 45288 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10111 ; free virtual = 45285 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10107 ; free virtual = 45282 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10105 ; free virtual = 45280 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10102 ; free virtual = 45277 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10099 ; free virtual = 45275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10096 ; free virtual = 45272 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10086 ; free virtual = 45263 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 10084 ; free virtual = 45262 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.227 ; gain = 0.000 ; free physical = 10052 ; free virtual = 45236 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10049 ; free virtual = 45233 Phase 3.6 Re-assign LUT pins Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10034 ; free virtual = 45219 Phase 3.7 Pipeline Register Optimization INFO: [Project 1-570] Preparing netlist for logic optimization 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.703 ; gain = 333.820 ; free physical = 10060 ; free virtual = 45246 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 10060 ; free virtual = 45247 Phase 1.3 Build Placer Netlist Model INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 10059 ; free virtual = 45245 Phase 1.4 Constrain Clocks/Macros Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10056 ; free virtual = 45243 Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 10056 ; free virtual = 45243 Writing bitstream ./design.bit... Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 10055 ; free virtual = 45242 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 10052 ; free virtual = 45241 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1993.270 ; gain = 510.531 ; free physical = 10045 ; free virtual = 45235 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1993.270 ; gain = 576.562 ; free physical = 10039 ; free virtual = 45229 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10032 ; free virtual = 45224 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10118 ; free virtual = 45312 Phase 4.2 Post Placement Cleanup Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.465 ; gain = 0.000 ; free physical = 10281 ; free virtual = 45476 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10302 ; free virtual = 45498 Phase 4.3 Placer Reporting INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10291 ; free virtual = 45487 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10308 ; free virtual = 45504 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10311 ; free virtual = 45485 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1483.734 ; gain = 0.000 ; free physical = 10312 ; free virtual = 45486 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1483.734 ; gain = 0.000 ; free physical = 10305 ; free virtual = 45479 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 10300 ; free virtual = 45474 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.199 ; gain = 623.949 ; free physical = 10296 ; free virtual = 45471 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Loading route data... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Processing options... Creating bitmap... Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:28:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2462.434 ; gain = 335.176 ; free physical = 9876 ; free virtual = 45050 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:28:47 2019... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1898.449 ; gain = 0.000 ; free physical = 9930 ; free virtual = 45104 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5615 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 10855 ; free virtual = 46029 Phase 1.3 Build Placer Netlist Model Bitstream size: 4243411 bytes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Config size: 1060815 words Number of configuration frames: 9996 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 10848 ; free virtual = 46021 Phase 1.4 Constrain Clocks/Macros DONE Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 10855 ; free virtual = 46029 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 10862 ; free virtual = 46035 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 10872 ; free virtual = 46046 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.492 ; gain = 514.531 ; free physical = 10881 ; free virtual = 46055 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.492 ; gain = 581.562 ; free physical = 10881 ; free virtual = 46055 synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 10881 ; free virtual = 46055 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design touch build/specimen_012/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_013 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 10746 ; free virtual = 45920 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 10746 ; free virtual = 45920 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 10207 ; free virtual = 45385 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:29:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:33 . Memory (MB): peak = 2474.121 ; gain = 334.105 ; free physical = 10115 ; free virtual = 45293 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:29:02 2019... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 11118 ; free virtual = 46297 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 11100 ; free virtual = 46279 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 11099 ; free virtual = 46278 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 11090 ; free virtual = 46269 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 22337 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_014 Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5858 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5907 Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.223 ; gain = 0.000 ; free physical = 10420 ; free virtual = 45599 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5936 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 510.531 ; free physical = 10406 ; free virtual = 45585 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 510.531 ; free physical = 10426 ; free virtual = 45605 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 510.531 ; free physical = 10425 ; free virtual = 45604 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 510.531 ; free physical = 10414 ; free virtual = 45593 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 510.531 ; free physical = 10406 ; free virtual = 45585 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.266 ; gain = 510.531 ; free physical = 10399 ; free virtual = 45579 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.266 ; gain = 577.562 ; free physical = 10399 ; free virtual = 45578 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 10167 ; free virtual = 45351 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 10160 ; free virtual = 45343 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 10156 ; free virtual = 45340 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10154 ; free virtual = 45338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 10103 ; free virtual = 45287 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 10102 ; free virtual = 45286 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 10102 ; free virtual = 45286 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 10102 ; free virtual = 45286 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 10102 ; free virtual = 45285 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 10103 ; free virtual = 45287 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 10103 ; free virtual = 45286 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10101 ; free virtual = 45285 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10100 ; free virtual = 45283 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10097 ; free virtual = 45281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10091 ; free virtual = 45274 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10095 ; free virtual = 45278 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Command: synth_design -top top --------------------------------------------------------------------------------- Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10095 ; free virtual = 45278 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10094 ; free virtual = 45278 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 10090 ; free virtual = 45273 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10090 ; free virtual = 45274 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:29:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.531 ; gain = 338.066 ; free physical = 10062 ; free virtual = 45246 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:29:12 2019... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 6083 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Project 1-570] Preparing netlist for logic optimization touch build/specimen_009/OK INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 10944 ; free virtual = 46128 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 10748 ; free virtual = 45932 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 10676 ; free virtual = 45859 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 10599 ; free virtual = 45783 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 10569 ; free virtual = 45753 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1463.711 ; gain = 0.000 ; free physical = 10569 ; free virtual = 45753 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 10386 ; free virtual = 45570 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10312 ; free virtual = 45496 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10310 ; free virtual = 45494 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10310 ; free virtual = 45494 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10304 ; free virtual = 45488 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 6244 Phase 1 Build RT Design | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.953 ; gain = 42.668 ; free physical = 10015 ; free virtual = 45199 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 9983 ; free virtual = 45167 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 9983 ; free virtual = 45167 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10276a5af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2087.371 ; gain = 62.086 ; free physical = 9859 ; free virtual = 45043 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9867 ; free virtual = 45051 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9862 ; free virtual = 45046 Phase 4 Rip-up And Reroute | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9860 ; free virtual = 45044 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9859 ; free virtual = 45043 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9857 ; free virtual = 45041 Phase 6 Post Hold Fix | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9856 ; free virtual = 45040 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.371 ; gain = 64.086 ; free physical = 9890 ; free virtual = 45074 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 9891 ; free virtual = 45075 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 9910 ; free virtual = 45097 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 9946 ; free virtual = 45133 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2130.160 ; gain = 136.891 ; free physical = 9944 ; free virtual = 45132 Writing placer database... Writing XDEF routing. Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.176 ; gain = 43.668 ; free physical = 9919 ; free virtual = 45115 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2130.160 ; gain = 0.000 ; free physical = 9892 ; free virtual = 45093 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.164 ; gain = 49.656 ; free physical = 9886 ; free virtual = 45088 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.164 ; gain = 49.656 ; free physical = 9885 ; free virtual = 45087 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2078.219 ; gain = 59.711 ; free physical = 9933 ; free virtual = 45143 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 9908 ; free virtual = 45104 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9869 ; free virtual = 45073 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9871 ; free virtual = 45077 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9872 ; free virtual = 45078 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9873 ; free virtual = 45079 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9874 ; free virtual = 45080 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9876 ; free virtual = 45082 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.219 ; gain = 61.711 ; free physical = 9924 ; free virtual = 45130 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.219 ; gain = 63.711 ; free physical = 9927 ; free virtual = 45134 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.219 ; gain = 63.711 ; free physical = 9931 ; free virtual = 45143 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.219 ; gain = 63.711 ; free physical = 9964 ; free virtual = 45178 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2121.008 ; gain = 134.516 ; free physical = 9961 ; free virtual = 45178 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2128.961 ; gain = 37.762 ; free physical = 9948 ; free virtual = 45171 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Running DRC as a precondition to command write_bitstream Phase 2.1 Fix Topology Constraints Writing placer database... Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.949 ; gain = 43.750 ; free physical = 9901 ; free virtual = 45128 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.949 ; gain = 43.750 ; free physical = 9901 ; free virtual = 45128 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1325.070 ; gain = 229.156 ; free physical = 9908 ; free virtual = 45116 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2121.008 ; gain = 0.000 ; free physical = 9893 ; free virtual = 45107 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 9931 ; free virtual = 45140 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9912 ; free virtual = 45145 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 9909 ; free virtual = 45142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 9966 ; free virtual = 45181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 9964 ; free virtual = 45179 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9945 ; free virtual = 45163 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9927 ; free virtual = 45149 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9919 ; free virtual = 45142 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9919 ; free virtual = 45142 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9919 ; free virtual = 45142 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9919 ; free virtual = 45142 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9919 ; free virtual = 45142 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9886 ; free virtual = 45112 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9886 ; free virtual = 45111 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9883 ; free virtual = 45109 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.004 ; gain = 62.805 ; free physical = 9917 ; free virtual = 45143 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2192.793 ; gain = 101.594 ; free physical = 9916 ; free virtual = 45143 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1325.070 ; gain = 229.156 ; free physical = 9923 ; free virtual = 45132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1333.098 ; gain = 237.184 ; free physical = 9928 ; free virtual = 45137 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 9878 ; free virtual = 45074 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9842 ; free virtual = 45039 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9843 ; free virtual = 45040 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9847 ; free virtual = 45044 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9848 ; free virtual = 45045 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9847 ; free virtual = 45045 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9846 ; free virtual = 45044 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9844 ; free virtual = 45042 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9843 ; free virtual = 45040 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 9850 ; free virtual = 45047 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 9618 ; free virtual = 44822 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.102 ; gain = 237.184 ; free physical = 9615 ; free virtual = 44819 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 9663 ; free virtual = 44869 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2192.793 ; gain = 0.000 ; free physical = 9354 ; free virtual = 44567 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1333.098 ; gain = 237.184 ; free physical = 9191 ; free virtual = 44383 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] Report RTL Partitions: INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: Launching helper process for spawning children vivado processes INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] INFO: Helper process launched with PID 6383 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] Loading data files... WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 9056 ; free virtual = 44248 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 9050 ; free virtual = 44242 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 9051 ; free virtual = 44243 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 9068 ; free virtual = 44260 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 9038 ; free virtual = 44230 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1347.062 ; gain = 251.152 ; free physical = 8770 ; free virtual = 43962 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8682 ; free virtual = 43875 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8676 ; free virtual = 43868 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8675 ; free virtual = 43868 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8673 ; free virtual = 43865 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8670 ; free virtual = 43862 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.242 ; gain = 468.531 ; free physical = 8668 ; free virtual = 43861 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 8668 ; free virtual = 43860 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 8685 ; free virtual = 43877 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 1337.070 ; gain = 241.152 ; free physical = 8646 ; free virtual = 43838 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 8625 ; free virtual = 43817 Starting Routing Task Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 8607 ; free virtual = 43800 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1341.098 ; gain = 245.184 ; free physical = 8558 ; free virtual = 43751 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1355.094 ; gain = 259.184 ; free physical = 8507 ; free virtual = 43699 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1341.098 ; gain = 245.184 ; free physical = 8500 ; free virtual = 43692 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1355.094 ; gain = 259.184 ; free physical = 8523 ; free virtual = 43715 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8348 ; free virtual = 43540 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8383 ; free virtual = 43576 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1341.102 ; gain = 245.184 ; free physical = 8351 ; free virtual = 43543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8331 ; free virtual = 43523 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8318 ; free virtual = 43511 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8304 ; free virtual = 43496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1341.102 ; gain = 245.184 ; free physical = 8303 ; free virtual = 43495 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8300 ; free virtual = 43492 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8296 ; free virtual = 43488 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8291 ; free virtual = 43483 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8289 ; free virtual = 43481 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.168 ; free physical = 8284 ; free virtual = 43476 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.090 ; gain = 254.168 ; free physical = 8283 ; free virtual = 43475 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8244 ; free virtual = 43436 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8228 ; free virtual = 43421 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8185 ; free virtual = 43377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8178 ; free virtual = 43370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8170 ; free virtual = 43363 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8166 ; free virtual = 43359 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8165 ; free virtual = 43357 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.070 ; gain = 267.160 ; free physical = 8162 ; free virtual = 43354 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1363.078 ; gain = 267.160 ; free physical = 8162 ; free virtual = 43354 INFO: [Project 1-571] Translating synthesized netlist Loading site data... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 8072 ; free virtual = 43267 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 8006 ; free virtual = 43198 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 7998 ; free virtual = 43190 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 7992 ; free virtual = 43184 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7976 ; free virtual = 43168 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7920 ; free virtual = 43112 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7917 ; free virtual = 43109 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading site data... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7896 ; free virtual = 43088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7873 ; free virtual = 43065 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7867 ; free virtual = 43059 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7864 ; free virtual = 43057 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7856 ; free virtual = 43049 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.078 ; gain = 253.160 ; free physical = 7851 ; free virtual = 43044 Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7853 ; free virtual = 43045 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1349.086 ; gain = 253.160 ; free physical = 7853 ; free virtual = 43045 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7849 ; free virtual = 43041 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading route data... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7846 ; free virtual = 43038 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7846 ; free virtual = 43038 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7845 ; free virtual = 43037 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7841 ; free virtual = 43033 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7833 ; free virtual = 43025 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7833 ; free virtual = 43025 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 7834 ; free virtual = 43026 Processing options... Creating bitmap... INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 7804 ; free virtual = 42996 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 7786 ; free virtual = 42979 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 7786 ; free virtual = 42979 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 7781 ; free virtual = 42974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.949 ; gain = 42.668 ; free physical = 7746 ; free virtual = 42939 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2075.938 ; gain = 49.656 ; free physical = 7708 ; free virtual = 42900 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2075.938 ; gain = 49.656 ; free physical = 7707 ; free virtual = 42899 INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.367 ; gain = 62.086 ; free physical = 7627 ; free virtual = 42819 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7603 ; free virtual = 42795 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7600 ; free virtual = 42793 Phase 4 Rip-up And Reroute | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7600 ; free virtual = 42793 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7601 ; free virtual = 42793 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7600 ; free virtual = 42793 Phase 6 Post Hold Fix | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7600 ; free virtual = 42793 Phase 7 Route finalize INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.367 ; gain = 63.086 ; free physical = 7592 ; free virtual = 42785 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.367 ; gain = 66.086 ; free physical = 7590 ; free virtual = 42783 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.367 ; gain = 66.086 ; free physical = 7590 ; free virtual = 42783 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.367 ; gain = 66.086 ; free physical = 7625 ; free virtual = 42817 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2131.156 ; gain = 136.891 ; free physical = 7620 ; free virtual = 42812 Writing placer database... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Writing XDEF routing. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2131.156 ; gain = 0.000 ; free physical = 7609 ; free virtual = 42805 Phase 1 Build RT Design | Checksum: 147c036e4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2057.938 ; gain = 93.668 ; free physical = 7591 ; free virtual = 42788 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c036e4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.926 ; gain = 97.656 ; free physical = 7564 ; free virtual = 42757 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c036e4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.926 ; gain = 97.656 ; free physical = 7564 ; free virtual = 42757 INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7466 ; free virtual = 42659 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7475 ; free virtual = 42668 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7470 ; free virtual = 42663 Phase 4 Rip-up And Reroute | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7470 ; free virtual = 42663 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7470 ; free virtual = 42663 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7470 ; free virtual = 42663 Phase 6 Post Hold Fix | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 7470 ; free virtual = 42663 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7449 ; free virtual = 42642 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 7447 ; free virtual = 42640 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 161e7cd46 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 7447 ; free virtual = 42640 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 7478 ; free virtual = 42672 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.770 ; gain = 178.516 ; free physical = 7478 ; free virtual = 42671 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 7459 ; free virtual = 42653 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Running DRC as a precondition to command write_bitstream INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 7382 ; free virtual = 42576 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Creating bitstream... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 7217 ; free virtual = 42411 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 7209 ; free virtual = 42402 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 7049 ; free virtual = 42243 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 7022 ; free virtual = 42216 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7026 ; free virtual = 42221 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7224 ; free virtual = 42421 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7233 ; free virtual = 42431 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7239 ; free virtual = 42437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7239 ; free virtual = 42437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7238 ; free virtual = 42436 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7237 ; free virtual = 42435 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7236 ; free virtual = 42435 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 7233 ; free virtual = 42432 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 7235 ; free virtual = 42434 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:30:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.453 ; gain = 0.000 ; free physical = 7292 ; free virtual = 42498 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 2462.113 ; gain = 341.105 ; free physical = 7293 ; free virtual = 42498 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:30:06 2019... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 8220 ; free virtual = 43425 Phase 1.3 Build Placer Netlist Model Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 8210 ; free virtual = 43416 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 8205 ; free virtual = 43411 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 8201 ; free virtual = 43407 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 8197 ; free virtual = 43403 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 8193 ; free virtual = 43398 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.496 ; gain = 584.562 ; free physical = 8191 ; free virtual = 43397 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:30:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2471.266 ; gain = 341.105 ; free physical = 8146 ; free virtual = 43353 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:30:07 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8226 ; free virtual = 43432 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:30:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.398 ; gain = 339.605 ; free physical = 9130 ; free virtual = 44337 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:30:08 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10088 ; free virtual = 45295 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10087 ; free virtual = 45294 touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.820 ; gain = 393.938 ; free physical = 9852 ; free virtual = 45060 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.840 ; gain = 393.953 ; free physical = 9797 ; free virtual = 45006 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 9832 ; free virtual = 45040 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Phase 1 Placer Initialization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.1 Placer Initialization Netlist Sorting Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1543.852 ; gain = 0.000 ; free physical = 9805 ; free virtual = 45013 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:01 . Memory (MB): peak = 1543.852 ; gain = 0.000 ; free physical = 9733 ; free virtual = 44942 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1544.871 ; gain = 0.000 ; free physical = 9515 ; free virtual = 44724 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Phase 1.1 Placer Initialization Netlist Sorting Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.81 . Memory (MB): peak = 1544.871 ; gain = 0.000 ; free physical = 9432 ; free virtual = 44641 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1543.867 ; gain = 0.000 ; free physical = 9426 ; free virtual = 44635 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1543.867 ; gain = 0.000 ; free physical = 9381 ; free virtual = 44590 Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.453 ; gain = 0.000 ; free physical = 9655 ; free virtual = 44868 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 9639 ; free virtual = 44852 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 9633 ; free virtual = 44846 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 9631 ; free virtual = 44844 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 9629 ; free virtual = 44842 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 9617 ; free virtual = 44830 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 9583 ; free virtual = 44796 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 584.562 ; free physical = 9581 ; free virtual = 44794 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:30:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2455.875 ; gain = 345.105 ; free physical = 9591 ; free virtual = 44808 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:30:25 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:30:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.262 ; gain = 339.105 ; free physical = 10373 ; free virtual = 45589 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:30:28 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 1 Build RT Design | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2057.926 ; gain = 93.668 ; free physical = 11268 ; free virtual = 46485 DONE Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.914 ; gain = 97.656 ; free physical = 11193 ; free virtual = 46410 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2061.914 ; gain = 97.656 ; free physical = 11192 ; free virtual = 46409 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11044 ; free virtual = 46262 Phase 3 Initial Routing touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 11070 ; free virtual = 46288 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11063 ; free virtual = 46281 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11062 ; free virtual = 46280 Phase 4 Rip-up And Reroute | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11061 ; free virtual = 46279 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11061 ; free virtual = 46279 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11061 ; free virtual = 46279 Phase 6 Post Hold Fix | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 11061 ; free virtual = 46279 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 11028 ; free virtual = 46246 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 11025 ; free virtual = 46243 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 11012 ; free virtual = 46230 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 11036 ; free virtual = 46254 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2110.758 ; gain = 178.516 ; free physical = 11028 ; free virtual = 46246 INFO: Launching helper process for spawning children vivado processes Writing placer database... Writing XDEF routing. INFO: Helper process launched with PID 7173 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2110.758 ; gain = 0.000 ; free physical = 10996 ; free virtual = 46216 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10960 ; free virtual = 46179 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10948 ; free virtual = 46166 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10930 ; free virtual = 46149 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10929 ; free virtual = 46148 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10928 ; free virtual = 46147 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10921 ; free virtual = 46139 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 10920 ; free virtual = 46139 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 7284 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7320 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.340 ; gain = 0.000 ; free physical = 9686 ; free virtual = 44905 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 9450 ; free virtual = 44669 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 9332 ; free virtual = 44551 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.359 ; gain = 0.000 ; free physical = 9250 ; free virtual = 44469 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.383 ; gain = 508.531 ; free physical = 9245 ; free virtual = 44464 Phase 1.3 Build Placer Netlist Model Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 9195 ; free virtual = 44414 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9171 ; free virtual = 44390 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 9174 ; free virtual = 44394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 9170 ; free virtual = 44390 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 9170 ; free virtual = 44389 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 9171 ; free virtual = 44390 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 9150 ; free virtual = 44370 Phase 1.3 Build Placer Netlist Model Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.402 ; gain = 507.531 ; free physical = 9020 ; free virtual = 44240 Phase 1.3 Build Placer Netlist Model INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 9050 ; free virtual = 44270 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 9029 ; free virtual = 44249 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 9028 ; free virtual = 44249 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 9021 ; free virtual = 44241 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.383 ; gain = 508.531 ; free physical = 8930 ; free virtual = 44150 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.383 ; gain = 508.531 ; free physical = 8917 ; free virtual = 44137 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.383 ; gain = 508.531 ; free physical = 8899 ; free virtual = 44119 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.383 ; gain = 508.531 ; free physical = 8885 ; free virtual = 44105 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.383 ; gain = 508.531 ; free physical = 8916 ; free virtual = 44136 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.383 ; gain = 575.562 ; free physical = 8910 ; free virtual = 44130 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 8780 ; free virtual = 44000 Phase 1.4 Constrain Clocks/Macros INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 8770 ; free virtual = 43989 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 8752 ; free virtual = 43972 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 8746 ; free virtual = 43966 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:16] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7465 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 8799 ; free virtual = 44019 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 8800 ; free virtual = 44020 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.402 ; gain = 507.531 ; free physical = 8735 ; free virtual = 43955 Phase 1.4 Constrain Clocks/Macros WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.402 ; gain = 507.531 ; free physical = 8696 ; free virtual = 43915 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.402 ; gain = 507.531 ; free physical = 8729 ; free virtual = 43953 Phase 2 Final Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8711 ; free virtual = 43931 --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.402 ; gain = 507.531 ; free physical = 8703 ; free virtual = 43924 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.402 ; gain = 507.531 ; free physical = 8741 ; free virtual = 43962 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.402 ; gain = 575.562 ; free physical = 8719 ; free virtual = 43946 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.180 ; gain = 43.668 ; free physical = 8722 ; free virtual = 43948 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.168 ; gain = 49.656 ; free physical = 8676 ; free virtual = 43902 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.168 ; gain = 49.656 ; free physical = 8675 ; free virtual = 43901 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8672 ; free virtual = 43893 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 8672 ; free virtual = 43892 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 8566 ; free virtual = 43786 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Number of Nodes with overlaps = 0 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8535 ; free virtual = 43756 Phase 1 Build RT Design Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8532 ; free virtual = 43752 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8531 ; free virtual = 43752 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8530 ; free virtual = 43750 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8530 ; free virtual = 43750 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8527 ; free virtual = 43748 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.473 ; gain = 62.961 ; free physical = 8500 ; free virtual = 43720 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 8500 ; free virtual = 43721 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.473 ; gain = 65.961 ; free physical = 8494 ; free virtual = 43715 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.473 ; gain = 65.961 ; free physical = 8531 ; free virtual = 43752 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2128.262 ; gain = 136.766 ; free physical = 8531 ; free virtual = 43752 Writing placer database... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2128.262 ; gain = 0.000 ; free physical = 8537 ; free virtual = 43760 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 8537 ; free virtual = 43760 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 8517 ; free virtual = 43737 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8512 ; free virtual = 43733 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 8420 ; free virtual = 43643 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.922 ; gain = 210.480 ; free physical = 8610 ; free virtual = 43836 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.922 ; gain = 210.480 ; free physical = 8764 ; free virtual = 43989 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8755 ; free virtual = 43980 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8754 ; free virtual = 43979 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8753 ; free virtual = 43978 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8746 ; free virtual = 43971 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8746 ; free virtual = 43971 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8745 ; free virtual = 43970 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8745 ; free virtual = 43970 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8745 ; free virtual = 43970 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 8744 ; free virtual = 43969 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 8747 ; free virtual = 43972 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7566 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8649 ; free virtual = 43874 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8649 ; free virtual = 43874 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8671 ; free virtual = 43896 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8671 ; free virtual = 43896 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8670 ; free virtual = 43895 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8670 ; free virtual = 43895 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8670 ; free virtual = 43895 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.898 ; gain = 218.457 ; free physical = 8670 ; free virtual = 43895 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.457 ; free physical = 8671 ; free virtual = 43896 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:30:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2454.863 ; gain = 344.105 ; free physical = 8373 ; free virtual = 43598 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:30:57 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words --------------------------------------------------------------------------------- Number of configuration frames: 9996 DONE Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9248 ; free virtual = 44473 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- touch build/specimen_012/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_015 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 9186 ; free virtual = 44411 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 9133 ; free virtual = 44358 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8985 ; free virtual = 44210 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 9034 ; free virtual = 44259 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 8961 ; free virtual = 44187 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8938 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 8923 ; free virtual = 44149 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 8919 ; free virtual = 44144 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8917 ; free virtual = 44142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 8936 ; free virtual = 44161 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8935 ; free virtual = 44161 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8932 ; free virtual = 44158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8938 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8945 ; free virtual = 44171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8948 ; free virtual = 44173 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 8938 ; free virtual = 44164 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 8939 ; free virtual = 44164 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Placer Task 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.922 ; gain = 323.039 ; free physical = 8942 ; free virtual = 44168 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 8942 ; free virtual = 44167 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1471.715 ; gain = 0.000 ; free physical = 8938 ; free virtual = 44164 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1469.953 ; gain = 0.000 ; free physical = 8816 ; free virtual = 44041 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1469.953 ; gain = 0.000 ; free physical = 8816 ; free virtual = 44041 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 8768 ; free virtual = 43993 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8540 ; free virtual = 43766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8504 ; free virtual = 43730 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8503 ; free virtual = 43730 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.180 ; gain = 42.668 ; free physical = 8440 ; free virtual = 43666 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8428 ; free virtual = 43654 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 8402 ; free virtual = 43628 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 8401 ; free virtual = 43627 Loading site data... Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 8314 ; free virtual = 43540 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8278 ; free virtual = 43506 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8277 ; free virtual = 43503 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8277 ; free virtual = 43503 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8277 ; free virtual = 43503 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8281 ; free virtual = 43507 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 8277 ; free virtual = 43503 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.473 ; gain = 62.961 ; free physical = 8273 ; free virtual = 43499 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 8274 ; free virtual = 43500 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.473 ; gain = 65.961 ; free physical = 8280 ; free virtual = 43506 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.473 ; gain = 65.961 ; free physical = 8318 ; free virtual = 43544 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.262 ; gain = 136.766 ; free physical = 8317 ; free virtual = 43543 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 8314 ; free virtual = 43540 --------------------------------------------------------------------------------- Writing placer database... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 8308 ; free virtual = 43534 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8301 ; free virtual = 43528 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2128.262 ; gain = 0.000 ; free physical = 8289 ; free virtual = 43518 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8232 ; free virtual = 43458 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8244 ; free virtual = 43470 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8219 ; free virtual = 43445 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8213 ; free virtual = 43440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8235 ; free virtual = 43461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8234 ; free virtual = 43461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8234 ; free virtual = 43460 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8231 ; free virtual = 43458 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 8231 ; free virtual = 43458 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 8218 ; free virtual = 43444 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 7984 ; free virtual = 43211 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 8086 ; free virtual = 43313 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 8273 ; free virtual = 43504 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8220 ; free virtual = 43451 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 8219 ; free virtual = 43449 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8204 ; free virtual = 43435 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8176 ; free virtual = 43407 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8167 ; free virtual = 43398 Phase 4 Rip-up And Reroute | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8167 ; free virtual = 43397 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8166 ; free virtual = 43396 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8165 ; free virtual = 43396 Phase 6 Post Hold Fix | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 8165 ; free virtual = 43396 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 8160 ; free virtual = 43390 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 8161 ; free virtual = 43392 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 8166 ; free virtual = 43396 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 8199 ; free virtual = 43429 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2109.766 ; gain = 177.516 ; free physical = 8199 ; free virtual = 43429 Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 8184 ; free virtual = 43416 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 8195 ; free virtual = 43425 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8189 ; free virtual = 43420 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8157 ; free virtual = 43388 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8151 ; free virtual = 43382 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 8119 ; free virtual = 43350 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 8118 ; free virtual = 43349 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8114 ; free virtual = 43345 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8112 ; free virtual = 43343 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8110 ; free virtual = 43341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8113 ; free virtual = 43344 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8111 ; free virtual = 43342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:31:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8112 ; free virtual = 43343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8113 ; free virtual = 43344 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8119 ; free virtual = 43350 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 8122 ; free virtual = 43353 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2463.438 ; gain = 335.176 ; free physical = 8123 ; free virtual = 43353 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:31:18 2019... INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 8231 ; free virtual = 43467 Loading data files... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.441 ; gain = 0.000 ; free physical = 8190 ; free virtual = 43427 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8206 ; free virtual = 43442 Phase 1.3 Build Placer Netlist Model INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7939 Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8208 ; free virtual = 43444 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8208 ; free virtual = 43445 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8203 ; free virtual = 43439 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8199 ; free virtual = 43436 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.484 ; gain = 516.531 ; free physical = 8199 ; free virtual = 43436 Phase 1.3 Build Placer Netlist Model Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 515.531 ; free physical = 8198 ; free virtual = 43434 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 8197 ; free virtual = 43434 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.484 ; gain = 516.531 ; free physical = 8197 ; free virtual = 43434 Phase 1.4 Constrain Clocks/Macros Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.484 ; gain = 516.531 ; free physical = 8196 ; free virtual = 43433 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.484 ; gain = 516.531 ; free physical = 8193 ; free virtual = 43430 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.484 ; gain = 516.531 ; free physical = 8189 ; free virtual = 43426 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.484 ; gain = 516.531 ; free physical = 8186 ; free virtual = 43422 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.484 ; gain = 580.562 ; free physical = 8185 ; free virtual = 43421 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 7864 ; free virtual = 43101 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 7719 ; free virtual = 42956 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 7709 ; free virtual = 42946 Creating bitstream... Loading site data... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 7306 ; free virtual = 42547 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.082 ; gain = 51.668 ; free physical = 7393 ; free virtual = 42634 Phase 1 Build RT Design | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.066 ; gain = 51.668 ; free physical = 7386 ; free virtual = 42626 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2146.055 ; gain = 61.656 ; free physical = 7142 ; free virtual = 42382 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2146.055 ; gain = 61.656 ; free physical = 7129 ; free virtual = 42370 Phase 2.1 Fix Topology Constraints | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2146.070 ; gain = 61.656 ; free physical = 7120 ; free virtual = 42361 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2146.070 ; gain = 61.656 ; free physical = 7108 ; free virtual = 42349 INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Number of Nodes with overlaps = 0 INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 7128 ; free virtual = 42369 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] Phase 2 Router Initialization | Checksum: 1a3bb806c WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7137 ; free virtual = 42378 Phase 3 Initial Routing WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] Number of Nodes with overlaps = 0 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Router Initialization | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7125 ; free virtual = 42366 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 7143 ; free virtual = 42384 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7144 ; free virtual = 42385 Number of Nodes with overlaps = 0 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 3 Initial Routing | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7140 ; free virtual = 42381 Phase 4.1 Global Iteration 0 | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7138 ; free virtual = 42379 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 7137 ; free virtual = 42379 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 7138 ; free virtual = 42379 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4 Rip-up And Reroute | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7137 ; free virtual = 42379 Phase 5 Delay and Skew Optimization Phase 4.1 Global Iteration 0 | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7137 ; free virtual = 42379 Phase 5 Delay and Skew Optimization | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7130 ; free virtual = 42372 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 4 Rip-up And Reroute | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7129 ; free virtual = 42371 Phase 5 Delay and Skew Optimization Phase 6.1 Hold Fix Iter | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7135 ; free virtual = 42376 Phase 5 Delay and Skew Optimization | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7135 ; free virtual = 42376 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6 Post Hold Fix | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7134 ; free virtual = 42375 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 6.1 Hold Fix Iter | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7133 ; free virtual = 42374 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 7129 ; free virtual = 42370 --------------------------------------------------------------------------------- Phase 6 Post Hold Fix | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7128 ; free virtual = 42369 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 7 Route finalize Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7070 ; free virtual = 42311 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7055 ; free virtual = 42296 Phase 9 Depositing Routes Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7090 ; free virtual = 42331 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7083 ; free virtual = 42324 Phase 9 Depositing Routes Phase 1 Build RT Design | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.086 ; gain = 49.668 ; free physical = 7053 ; free virtual = 42294 Phase 9 Depositing Routes | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7041 ; free virtual = 42282 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 7083 ; free virtual = 42324 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2219.773 ; gain = 167.391 ; free physical = 7082 ; free virtual = 42323 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 9 Depositing Routes | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7074 ; free virtual = 42315 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2181.000 ; gain = 96.586 ; free physical = 7117 ; free virtual = 42358 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:48 . Memory (MB): peak = 2219.789 ; gain = 167.391 ; free physical = 7117 ; free virtual = 42358 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:31:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 2.1 Fix Topology Constraints 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2462.438 ; gain = 334.176 ; free physical = 7090 ; free virtual = 42332 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:31:37 2019... Phase 2.1 Fix Topology Constraints | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2144.074 ; gain = 59.656 ; free physical = 7080 ; free virtual = 42322 Phase 2.2 Pre Route Cleanup Writing placer database... Phase 2.2 Pre Route Cleanup | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2144.074 ; gain = 59.656 ; free physical = 7060 ; free virtual = 42302 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 7045 ; free virtual = 42288 Phase 1.3 Build Placer Netlist Model Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7708 ; free virtual = 42968 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 7733 ; free virtual = 42998 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7807 ; free virtual = 43076 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7941 ; free virtual = 43211 Phase 4 Rip-up And Reroute | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7970 ; free virtual = 43240 Phase 5 Delay and Skew Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. Phase 5 Delay and Skew Optimization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7998 ; free virtual = 43268 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 6.1 Hold Fix Iter | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7996 ; free virtual = 43268 Phase 6 Post Hold Fix | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7995 ; free virtual = 43266 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7989 ; free virtual = 43267 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 7984 ; free virtual = 43264 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 8037 ; free virtual = 43322 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.004 ; gain = 95.586 ; free physical = 8075 ; free virtual = 43360 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2218.793 ; gain = 166.391 ; free physical = 8075 ; free virtual = 43360 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 8050 ; free virtual = 43341 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 8049 ; free virtual = 43341 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 8049 ; free virtual = 43340 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 8049 ; free virtual = 43340 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 8048 ; free virtual = 43340 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 8037 ; free virtual = 43329 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 8035 ; free virtual = 43327 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.773 ; gain = 0.000 ; free physical = 7983 ; free virtual = 43293 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 7982 ; free virtual = 43294 Phase 1.4 Constrain Clocks/Macros Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.789 ; gain = 0.000 ; free physical = 7980 ; free virtual = 43298 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 7978 ; free virtual = 43297 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 7974 ; free virtual = 43295 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" Phase 1 Build RT Design ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2219.789 ; gain = 0.000 ; free physical = 7928 ; free virtual = 43228 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2219.773 ; gain = 0.000 ; free physical = 7939 ; free virtual = 43212 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:31:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.871 ; gain = 344.105 ; free physical = 7938 ; free virtual = 43211 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:31:42 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.793 ; gain = 0.000 ; free physical = 8755 ; free virtual = 44040 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 8649 ; free virtual = 43940 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 8640 ; free virtual = 43932 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2218.793 ; gain = 0.000 ; free physical = 8654 ; free virtual = 43918 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8640 ; free virtual = 43904 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9137 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8663 ; free virtual = 43928 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8666 ; free virtual = 43931 Phase 3.2 Commit Most Macros & LUTRAMs Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8654 ; free virtual = 43919 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8652 ; free virtual = 43917 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8650 ; free virtual = 43915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8650 ; free virtual = 43915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8649 ; free virtual = 43914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8649 ; free virtual = 43914 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8647 ; free virtual = 43912 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 8645 ; free virtual = 43910 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8646 ; free virtual = 43911 INFO: [Project 1-571] Translating synthesized netlist Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8448 ; free virtual = 43713 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8378 ; free virtual = 43643 Phase 3.4 Pipeline Register Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8369 ; free virtual = 43634 Phase 3.5 Small Shape Detail Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 8370 ; free virtual = 43635 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 8347 ; free virtual = 43613 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 8346 ; free virtual = 43611 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 8347 ; free virtual = 43612 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 8366 ; free virtual = 43631 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 8383 ; free virtual = 43648 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 8384 ; free virtual = 43649 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 8383 ; free virtual = 43648 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8275 ; free virtual = 43540 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8234 ; free virtual = 43499 Phase 3.7 Pipeline Register Optimization WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8216 ; free virtual = 43481 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8205 ; free virtual = 43470 Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8164 ; free virtual = 43429 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8118 ; free virtual = 43383 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8095 ; free virtual = 43360 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8080 ; free virtual = 43346 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8069 ; free virtual = 43335 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2107.203 ; gain = 560.254 ; free physical = 8068 ; free virtual = 43334 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2107.203 ; gain = 639.957 ; free physical = 8067 ; free virtual = 43333 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 7968 ; free virtual = 43233 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Starting Placer Task Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.953 ; gain = 0.000 ; free physical = 7833 ; free virtual = 43099 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1470.953 ; gain = 0.000 ; free physical = 7831 ; free virtual = 43096 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 7657 ; free virtual = 42922 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9407 Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2062.930 ; gain = 43.668 ; free physical = 6272 ; free virtual = 41537 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 6225 ; free virtual = 41491 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.918 ; gain = 48.656 ; free physical = 6220 ; free virtual = 41485 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9458 Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2078.973 ; gain = 59.711 ; free physical = 6096 ; free virtual = 41362 Phase 3 Initial Routing INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6043 ; free virtual = 41309 Loading route data... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6078 ; free virtual = 41344 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6079 ; free virtual = 41344 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6079 ; free virtual = 41345 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6077 ; free virtual = 41342 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6074 ; free virtual = 41340 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Processing options... Creating bitmap... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 6095 ; free virtual = 41363 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 6095 ; free virtual = 41363 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 6094 ; free virtual = 41362 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 6130 ; free virtual = 41398 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2121.762 ; gain = 134.516 ; free physical = 6130 ; free virtual = 41399 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2064.168 ; gain = 45.668 ; free physical = 6115 ; free virtual = 41386 Writing placer database... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.156 ; gain = 50.656 ; free physical = 6077 ; free virtual = 41350 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.156 ; gain = 50.656 ; free physical = 6077 ; free virtual = 41350 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.60 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 6062 ; free virtual = 41339 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2079.211 ; gain = 60.711 ; free physical = 5928 ; free virtual = 41214 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5769 ; free virtual = 41056 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5765 ; free virtual = 41052 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5765 ; free virtual = 41052 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5763 ; free virtual = 41049 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5760 ; free virtual = 41047 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5763 ; free virtual = 41049 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2081.211 ; gain = 62.711 ; free physical = 5778 ; free virtual = 41065 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2083.211 ; gain = 64.711 ; free physical = 5780 ; free virtual = 41067 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 5841 ; free virtual = 41109 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.211 ; gain = 64.711 ; free physical = 5839 ; free virtual = 41107 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.211 ; gain = 64.711 ; free physical = 5876 ; free virtual = 41144 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2122.000 ; gain = 135.516 ; free physical = 5877 ; free virtual = 41144 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2122.000 ; gain = 0.000 ; free physical = 5919 ; free virtual = 41189 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.441 ; gain = 0.000 ; free physical = 5939 ; free virtual = 41212 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 520.531 ; free physical = 5851 ; free virtual = 41138 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 520.531 ; free physical = 5853 ; free virtual = 41140 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 520.531 ; free physical = 5862 ; free virtual = 41149 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 520.531 ; free physical = 5858 ; free virtual = 41146 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 520.531 ; free physical = 5867 ; free virtual = 41154 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.484 ; gain = 520.531 ; free physical = 5900 ; free virtual = 41188 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.484 ; gain = 584.562 ; free physical = 5898 ; free virtual = 41185 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 5791 ; free virtual = 41059 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 5790 ; free virtual = 41058 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:19 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 5627 ; free virtual = 40895 --------------------------------------------------------------------------------- Loading data files... Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] Creating bitstream... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 5272 ; free virtual = 40540 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 5165 ; free virtual = 40433 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 5941 ; free virtual = 41222 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 5935 ; free virtual = 41216 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 5820 ; free virtual = 41100 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:32:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:06 ; elapsed = 00:00:53 . Memory (MB): peak = 2607.895 ; gain = 388.121 ; free physical = 5821 ; free virtual = 41102 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:32:34 2019... Loading site data... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:32:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:06 ; elapsed = 00:00:53 . Memory (MB): peak = 2608.910 ; gain = 389.121 ; free physical = 5929 ; free virtual = 41208 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:32:35 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Loading route data... DONE Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Phase 1 Build RT Design | Checksum: 1307d6b8e Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 8026 ; free virtual = 43305 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1307d6b8e Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 7984 ; free virtual = 43264 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1307d6b8e Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 7984 ; free virtual = 43264 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7980 ; free virtual = 43259 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7969 ; free virtual = 43248 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7942 ; free virtual = 43222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7945 ; free virtual = 43225 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7934 ; free virtual = 43214 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7931 ; free virtual = 43211 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7929 ; free virtual = 43209 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7926 ; free virtual = 43207 Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 7927 ; free virtual = 43208 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6d37d05e Time (s): cpu = 00:00:40 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7926 ; free virtual = 43206 Phase 3 Initial Routing INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:32:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:06 ; elapsed = 00:00:51 . Memory (MB): peak = 2606.914 ; gain = 388.121 ; free physical = 7850 ; free virtual = 43130 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:32:36 2019... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7852 ; free virtual = 43131 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7853 ; free virtual = 43132 Phase 4 Rip-up And Reroute | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7853 ; free virtual = 43131 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7853 ; free virtual = 43131 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7852 ; free virtual = 43131 Phase 6 Post Hold Fix | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7852 ; free virtual = 43131 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7854 ; free virtual = 43138 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 7860 ; free virtual = 43144 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 7905 ; free virtual = 43189 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 7949 ; free virtual = 43233 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 7951 ; free virtual = 43235 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 8273 ; free virtual = 43559 Loading site data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:36 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8963 ; free virtual = 44256 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8863 ; free virtual = 44156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8861 ; free virtual = 44154 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 8849 ; free virtual = 44142 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 8822 ; free virtual = 44115 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 8822 ; free virtual = 44114 Loading data files... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2086.250 ; gain = 59.961 ; free physical = 8765 ; free virtual = 44058 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8697 ; free virtual = 43990 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8679 ; free virtual = 43972 Phase 4 Rip-up And Reroute | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8676 ; free virtual = 43968 Phase 5 Delay and Skew Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 5 Delay and Skew Optimization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8672 ; free virtual = 43965 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8666 ; free virtual = 43959 Phase 6 Post Hold Fix | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8665 ; free virtual = 43958 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Creating bitstream... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2089.250 ; gain = 62.961 ; free physical = 8638 ; free virtual = 43931 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 8634 ; free virtual = 43927 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:55 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 8608 ; free virtual = 43901 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:55 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 8643 ; free virtual = 43936 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2130.039 ; gain = 135.766 ; free physical = 8643 ; free virtual = 43936 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] Writing placer database... Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 8691 ; free virtual = 43993 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8947 ; free virtual = 44246 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2131.098 ; gain = 23.895 ; free physical = 9036 ; free virtual = 44335 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2138.086 ; gain = 30.883 ; free physical = 8998 ; free virtual = 44299 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2138.086 ; gain = 30.883 ; free physical = 8998 ; free virtual = 44299 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 8889 ; free virtual = 44210 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9044 ; free virtual = 44367 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9145 ; free virtual = 44468 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9146 ; free virtual = 44469 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9147 ; free virtual = 44470 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9148 ; free virtual = 44471 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9149 ; free virtual = 44472 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9146 ; free virtual = 44469 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9145 ; free virtual = 44468 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9139 ; free virtual = 44462 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:54 . Memory (MB): peak = 2156.141 ; gain = 48.938 ; free physical = 9172 ; free virtual = 44494 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:56 . Memory (MB): peak = 2194.930 ; gain = 87.727 ; free physical = 9169 ; free virtual = 44492 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 9187 ; free virtual = 44490 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 9185 ; free virtual = 44488 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:32:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:45 . Memory (MB): peak = 1335.070 ; gain = 239.152 ; free physical = 9206 ; free virtual = 44513 --------------------------------------------------------------------------------- 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2460.867 ; gain = 339.105 ; free physical = 9205 ; free virtual = 44512 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:32:50 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:32:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2463.105 ; gain = 341.105 ; free physical = 9764 ; free virtual = 45088 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:32:53 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.930 ; gain = 0.000 ; free physical = 9833 ; free virtual = 45160 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:48 . Memory (MB): peak = 1340.102 ; gain = 244.184 ; free physical = 10598 ; free virtual = 45925 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading site data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:48 . Memory (MB): peak = 1340.102 ; gain = 244.184 ; free physical = 10659 ; free virtual = 45965 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 21992 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 10543 ; free virtual = 45849 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:50 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10459 ; free virtual = 45765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10418 ; free virtual = 45725 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10417 ; free virtual = 45724 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10354 ; free virtual = 45661 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10348 ; free virtual = 45655 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10338 ; free virtual = 45645 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10339 ; free virtual = 45646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10336 ; free virtual = 45643 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 10331 ; free virtual = 45638 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:52 . Memory (MB): peak = 1348.086 ; gain = 252.160 ; free physical = 10329 ; free virtual = 45636 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 10321 ; free virtual = 45628 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:47 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 10247 ; free virtual = 45553 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading data files... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:48 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10574 ; free virtual = 45884 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10060 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10066 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10113 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:49 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10441 ; free virtual = 45751 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:49 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10420 ; free virtual = 45731 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:19 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 10422 ; free virtual = 45733 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10387 ; free virtual = 45697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10395 ; free virtual = 45706 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10378 ; free virtual = 45689 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10374 ; free virtual = 45684 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Command: report_drc (run_mandatory_drcs) for: placer_checks Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ INFO: [DRC 23-27] Running DRC with 8 threads Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10371 ; free virtual = 45682 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 10365 ; free virtual = 45676 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.086 ; gain = 256.160 ; free physical = 10365 ; free virtual = 45676 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:33:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2454.867 ; gain = 344.105 ; free physical = 10347 ; free virtual = 45658 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:33:02 2019... Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.168 ; gain = 44.668 ; free physical = 11189 ; free virtual = 46500 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1 Placer Initialization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.156 ; gain = 50.656 ; free physical = 11159 ; free virtual = 46469 Phase 2.2 Pre Route Cleanup Phase 1.1 Placer Initialization Netlist Sorting Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.156 ; gain = 50.656 ; free physical = 11187 ; free virtual = 46497 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.863 ; gain = 0.000 ; free physical = 11180 ; free virtual = 46490 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1554.863 ; gain = 0.000 ; free physical = 11171 ; free virtual = 46481 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.461 ; gain = 60.961 ; free physical = 11092 ; free virtual = 46403 Phase 3 Initial Routing INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11015 ; free virtual = 46326 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11014 ; free virtual = 46325 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11014 ; free virtual = 46324 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11013 ; free virtual = 46324 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11013 ; free virtual = 46324 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11013 ; free virtual = 46324 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 11070 ; free virtual = 46381 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.461 ; gain = 64.961 ; free physical = 11067 ; free virtual = 46378 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.461 ; gain = 64.961 ; free physical = 11059 ; free virtual = 46369 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.461 ; gain = 64.961 ; free physical = 11096 ; free virtual = 46406 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2127.250 ; gain = 135.766 ; free physical = 11096 ; free virtual = 46406 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2127.250 ; gain = 0.000 ; free physical = 11071 ; free virtual = 46385 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 10474 ; free virtual = 45786 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10440 ; free virtual = 45751 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 10425 ; free virtual = 45737 --------------------------------------------------------------------------------- Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2] Creating bitstream... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:216] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:936] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2088] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2208] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2328] INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2352] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] Writing bitstream ./design.bit... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10197 ; free virtual = 45512 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10280 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10318 ; free virtual = 45633 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10324 ; free virtual = 45639 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:48] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:96] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10432 ; free virtual = 45748 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:115] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:336] Report RTL Partitions: +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:336] | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:432] No constraint files found. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:480] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:504] Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:504] --------------------------------------------------------------------------------- Hierarchical RTL Component report WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:523] --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:528] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:528] --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1632] INFO: [Vivado 12-1842] Bitgen Completed Successfully. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1704] INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10349 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:33:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 2468.145 ; gain = 338.105 ; free physical = 10502 ; free virtual = 45822 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:33:18 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:33:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2532.035 ; gain = 337.105 ; free physical = 11362 ; free virtual = 46683 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:33:20 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:17 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 12226 ; free virtual = 47547 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12136 ; free virtual = 47459 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading route data... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 12093 ; free virtual = 47416 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12085 ; free virtual = 47408 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 12006 ; free virtual = 47329 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11843 ; free virtual = 47165 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11842 ; free virtual = 47164 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11841 ; free virtual = 47163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11840 ; free virtual = 47163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11840 ; free virtual = 47162 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11839 ; free virtual = 47161 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11838 ; free virtual = 47160 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11835 ; free virtual = 47158 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11836 ; free virtual = 47158 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-571] Translating synthesized netlist Starting Placer Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1556.867 ; gain = 0.000 ; free physical = 11768 ; free virtual = 47090 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1556.867 ; gain = 0.000 ; free physical = 11734 ; free virtual = 47057 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Launching helper process for spawning children vivado processes INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] INFO: Helper process launched with PID 10539 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 11761 ; free virtual = 47085 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 11765 ; free virtual = 47087 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 11790 ; free virtual = 47113 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 11806 ; free virtual = 47129 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Device 21-403] Loading part xc7z020clg400-1 Creating bitstream... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 11798 ; free virtual = 47123 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 11614 ; free virtual = 46938 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 11598 ; free virtual = 46942 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2] INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:18 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 11714 ; free virtual = 47045 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 11690 ; free virtual = 47043 Phase 1.3 Build Placer Netlist Model INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:229] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:312] Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 11539 ; free virtual = 46865 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:330] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3632] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4978] Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 11545 ; free virtual = 46871 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5061] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5227] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5974] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6140] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 11541 ; free virtual = 46867 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6223] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 11592 ; free virtual = 46921 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 11889 ; free virtual = 47239 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 11835 ; free virtual = 47186 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 11832 ; free virtual = 47182 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 11818 ; free virtual = 47149 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 11819 ; free virtual = 47149 Phase 1 Placer Initialization --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting INFO: [Device 21-403] Loading part xc7z020clg400-1 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1562.867 ; gain = 0.000 ; free physical = 11831 ; free virtual = 47161 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1562.867 ; gain = 0.000 ; free physical = 11817 ; free virtual = 47148 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 11814 ; free virtual = 47145 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 11814 ; free virtual = 47144 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 11794 ; free virtual = 47124 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 11650 ; free virtual = 46981 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 11639 ; free virtual = 46970 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 11622 ; free virtual = 46953 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 11607 ; free virtual = 46938 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 497.531 ; free physical = 11615 ; free virtual = 46946 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 11611 ; free virtual = 46941 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:33:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2463.426 ; gain = 336.176 ; free physical = 11583 ; free virtual = 46914 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:33:33 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 15 #of bits: 12552 #of tags: 110 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_013 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 12468 ; free virtual = 47799 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 12296 ; free virtual = 47627 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 12277 ; free virtual = 47609 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12399 ; free virtual = 47730 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 12402 ; free virtual = 47733 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.062 ; gain = 242.152 ; free physical = 12398 ; free virtual = 47730 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12386 ; free virtual = 47718 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12385 ; free virtual = 47717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- No constraint files found. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12380 ; free virtual = 47712 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12377 ; free virtual = 47709 Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12373 ; free virtual = 47705 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12371 ; free virtual = 47703 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12369 ; free virtual = 47700 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12366 ; free virtual = 47698 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 12367 ; free virtual = 47699 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12278 ; free virtual = 47611 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 12260 ; free virtual = 47592 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12259 ; free virtual = 47591 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 12247 ; free virtual = 47580 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 12139 ; free virtual = 47477 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 12121 ; free virtual = 47454 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 12110 ; free virtual = 47442 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 12088 ; free virtual = 47420 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12077 ; free virtual = 47409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.094 ; gain = 246.184 ; free physical = 12053 ; free virtual = 47385 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.094 ; gain = 246.184 ; free physical = 11985 ; free virtual = 47317 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11942 ; free virtual = 47274 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11940 ; free virtual = 47272 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11940 ; free virtual = 47272 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11936 ; free virtual = 47268 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11935 ; free virtual = 47267 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11934 ; free virtual = 47266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11933 ; free virtual = 47265 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11932 ; free virtual = 47265 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 11922 ; free virtual = 47254 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 11924 ; free virtual = 47256 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 11886 ; free virtual = 47218 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11736 ; free virtual = 47068 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11701 ; free virtual = 47034 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11682 ; free virtual = 47014 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11617 ; free virtual = 46949 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11615 ; free virtual = 46947 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl --------------------------------------------------------------------------------- # source "$::env(XRAY_DIR)/utils/utils.tcl" Start Handling Custom Attributes --------------------------------------------------------------------------------- ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11628 ; free virtual = 46960 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11627 ; free virtual = 46959 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11624 ; free virtual = 46957 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 11620 ; free virtual = 46953 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 11621 ; free virtual = 46954 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 11588 ; free virtual = 46921 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 11588 ; free virtual = 46921 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11491 ; free virtual = 46824 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11443 ; free virtual = 46776 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 11423 ; free virtual = 46755 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11420 ; free virtual = 46752 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: Helper process launched with PID 10819 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11415 ; free virtual = 46747 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11408 ; free virtual = 46741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11395 ; free virtual = 46728 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11392 ; free virtual = 46725 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 11388 ; free virtual = 46721 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 11390 ; free virtual = 46723 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10838 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11169 ; free virtual = 46502 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11163 ; free virtual = 46496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11160 ; free virtual = 46493 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 11141 ; free virtual = 46474 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11117 ; free virtual = 46450 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11117 ; free virtual = 46450 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11117 ; free virtual = 46449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11116 ; free virtual = 46449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11116 ; free virtual = 46449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11116 ; free virtual = 46449 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11116 ; free virtual = 46449 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11116 ; free virtual = 46449 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 11118 ; free virtual = 46450 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 11111 ; free virtual = 46444 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Starting Placer Task WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 10906 ; free virtual = 46238 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 10931 ; free virtual = 46263 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 10380 ; free virtual = 45713 Phase 1.4 Constrain Clocks/Macros INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 10361 ; free virtual = 45693 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 10359 ; free virtual = 45691 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 10334 ; free virtual = 45667 Phase 2 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 10324 ; free virtual = 45656 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 10290 ; free virtual = 45623 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 10241 ; free virtual = 45573 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 10232 ; free virtual = 45565 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 10244 ; free virtual = 45576 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10234 ; free virtual = 45567 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10232 ; free virtual = 45564 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10221 ; free virtual = 45553 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10219 ; free virtual = 45552 Phase 2 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10218 ; free virtual = 45551 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10219 ; free virtual = 45552 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 10218 ; free virtual = 45551 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10080 ; free virtual = 45413 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 10079 ; free virtual = 45412 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 10104 ; free virtual = 45437 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 10104 ; free virtual = 45436 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.398 ; gain = 489.531 ; free physical = 10101 ; free virtual = 45434 Phase 1.3 Build Placer Netlist Model report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9907 ; free virtual = 45240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9901 ; free virtual = 45234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9901 ; free virtual = 45234 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9863 ; free virtual = 45196 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11016 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:16] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.398 ; gain = 489.531 ; free physical = 9726 ; free virtual = 45059 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.398 ; gain = 489.531 ; free physical = 9699 ; free virtual = 45032 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 489.531 ; free physical = 9628 ; free virtual = 44961 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 489.531 ; free physical = 9623 ; free virtual = 44957 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 489.531 ; free physical = 9647 ; free virtual = 44980 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 9656 ; free virtual = 44989 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9604 ; free virtual = 44938 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9329 ; free virtual = 44663 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9326 ; free virtual = 44660 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 9323 ; free virtual = 44657 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9173 ; free virtual = 44507 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9170 ; free virtual = 44503 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9169 ; free virtual = 44503 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9169 ; free virtual = 44503 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9169 ; free virtual = 44502 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9169 ; free virtual = 44503 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 9169 ; free virtual = 44503 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1270.285 ; gain = 174.672 ; free physical = 8983 ; free virtual = 44317 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8981 ; free virtual = 44315 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8961 ; free virtual = 44295 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8954 ; free virtual = 44288 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44253 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44253 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44252 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44252 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44253 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8919 ; free virtual = 44253 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 8921 ; free virtual = 44255 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 8902 ; free virtual = 44236 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.820 ; gain = 393.938 ; free physical = 8919 ; free virtual = 44253 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 8528 ; free virtual = 43862 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8503 ; free virtual = 43837 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8497 ; free virtual = 43831 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.227 ; gain = 0.000 ; free physical = 8522 ; free virtual = 43856 Starting Placer Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8480 ; free virtual = 43814 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1555.863 ; gain = 0.000 ; free physical = 8479 ; free virtual = 43813 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Placer Initialization --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 8463 ; free virtual = 43797 Phase 1.3 Build Placer Netlist Model Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1556.852 ; gain = 0.000 ; free physical = 8463 ; free virtual = 43797 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.62 . Memory (MB): peak = 1555.863 ; gain = 0.000 ; free physical = 8461 ; free virtual = 43795 Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 8461 ; free virtual = 43795 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 8457 ; free virtual = 43791 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 8444 ; free virtual = 43777 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 8439 ; free virtual = 43773 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.270 ; gain = 511.531 ; free physical = 8438 ; free virtual = 43772 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.270 ; gain = 576.562 ; free physical = 8438 ; free virtual = 43772 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.69 . Memory (MB): peak = 1556.852 ; gain = 0.000 ; free physical = 8437 ; free virtual = 43770 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8300 ; free virtual = 43634 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8292 ; free virtual = 43626 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8256 ; free virtual = 43590 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8238 ; free virtual = 43572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8234 ; free virtual = 43568 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8229 ; free virtual = 43563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8227 ; free virtual = 43561 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8200 ; free virtual = 43534 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 8200 ; free virtual = 43534 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 7882 ; free virtual = 43216 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 7852 ; free virtual = 43186 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:16] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7829 ; free virtual = 43163 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7827 ; free virtual = 43161 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7826 ; free virtual = 43160 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7824 ; free virtual = 43158 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7823 ; free virtual = 43157 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 7825 ; free virtual = 43159 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 7826 ; free virtual = 43160 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:7] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7773 ; free virtual = 43108 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7782 ; free virtual = 43116 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7812 ; free virtual = 43146 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7784 ; free virtual = 43119 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 7782 ; free virtual = 43117 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.078 ; gain = 50.668 ; free physical = 7553 ; free virtual = 42887 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 7522 ; free virtual = 42856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 7479 ; free virtual = 42814 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 7477 ; free virtual = 42811 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7415 ; free virtual = 42749 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7392 ; free virtual = 42727 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7390 ; free virtual = 42724 Phase 4 Rip-up And Reroute | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7388 ; free virtual = 42723 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7388 ; free virtual = 42722 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7387 ; free virtual = 42722 Phase 6 Post Hold Fix | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7387 ; free virtual = 42721 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7377 ; free virtual = 42711 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 7375 ; free virtual = 42709 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.871 ; gain = 96.461 ; free physical = 7360 ; free virtual = 42695 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.871 ; gain = 96.461 ; free physical = 7405 ; free virtual = 42740 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2219.660 ; gain = 167.266 ; free physical = 7404 ; free virtual = 42739 Writing placer database... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 7415 ; free virtual = 42753 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 7270 ; free virtual = 42620 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 7258 ; free virtual = 42610 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 7245 ; free virtual = 42597 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 7239 ; free virtual = 42592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7203 ; free virtual = 42562 --------------------------------------------------------------------------------- Writing XDEF routing. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Start Final Netlist Cleanup Writing XDEF routing special nets. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.660 ; gain = 0.000 ; free physical = 7198 ; free virtual = 42560 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2219.660 ; gain = 0.000 ; free physical = 7201 ; free virtual = 42538 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7198 ; free virtual = 42536 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7196 ; free virtual = 42534 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7182 ; free virtual = 42520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7180 ; free virtual = 42517 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7176 ; free virtual = 42514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7175 ; free virtual = 42512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7174 ; free virtual = 42512 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 7170 ; free virtual = 42508 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 7174 ; free virtual = 42512 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.340 ; gain = 0.000 ; free physical = 6414 ; free virtual = 41752 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 6400 ; free virtual = 41738 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.383 ; gain = 495.531 ; free physical = 6216 ; free virtual = 41554 Phase 1.3 Build Placer Netlist Model Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 496.531 ; free physical = 6213 ; free virtual = 41551 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Build RT Design | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.082 ; gain = 50.668 ; free physical = 5976 ; free virtual = 41314 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 5975 ; free virtual = 41313 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2145.070 ; gain = 60.656 ; free physical = 5891 ; free virtual = 41229 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2145.070 ; gain = 60.656 ; free physical = 5886 ; free virtual = 41224 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5861 ; free virtual = 41199 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5884 ; free virtual = 41222 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5883 ; free virtual = 41221 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5883 ; free virtual = 41221 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5882 ; free virtual = 41220 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5890 ; free virtual = 41228 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 5893 ; free virtual = 41231 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 5869 ; free virtual = 41206 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 5832 ; free virtual = 41169 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 5831 ; free virtual = 41169 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5802 ; free virtual = 41139 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5797 ; free virtual = 41135 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5770 ; free virtual = 41107 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5755 ; free virtual = 41093 Phase 4 Rip-up And Reroute | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5749 ; free virtual = 41087 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5742 ; free virtual = 41080 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 6.1 Hold Fix Iter | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5744 ; free virtual = 41082 Phase 6 Post Hold Fix | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5749 ; free virtual = 41086 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5757 ; free virtual = 41095 Phase 7 Route finalize Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5764 ; free virtual = 41102 Phase 4 Rip-up And Reroute | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5764 ; free virtual = 41102 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5764 ; free virtual = 41102 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5764 ; free virtual = 41102 Phase 6 Post Hold Fix | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 5764 ; free virtual = 41102 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 5762 ; free virtual = 41100 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 5762 ; free virtual = 41100 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 5766 ; free virtual = 41103 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 5811 ; free virtual = 41149 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 5819 ; free virtual = 41157 Phase 7 Route finalize | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5850 ; free virtual = 41188 Phase 8 Verifying routed nets Verification completed successfully INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.254 ; gain = 384.367 ; free physical = 5865 ; free virtual = 41203 Phase 8 Verifying routed nets | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5865 ; free virtual = 41203 Phase 9 Depositing Routes Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Writing placer database... INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 5861 ; free virtual = 41201 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5755 ; free virtual = 41094 INFO: [Route 35-16] Router Completed Successfully report_drc (run_mandatory_drcs) completed successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 5796 ; free virtual = 41134 Routing Is Done. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2218.789 ; gain = 166.391 ; free physical = 5799 ; free virtual = 41137 Starting Routing Task Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 496.531 ; free physical = 5775 ; free virtual = 41113 Phase 1.4 Constrain Clocks/Macros Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.383 ; gain = 495.531 ; free physical = 5771 ; free virtual = 41109 Phase 1.4 Constrain Clocks/Macros Phase 1 Build RT Design Loading data files... Writing placer database... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.383 ; gain = 495.531 ; free physical = 5751 ; free virtual = 41091 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 496.531 ; free physical = 5744 ; free virtual = 41085 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.383 ; gain = 495.531 ; free physical = 5749 ; free virtual = 41091 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.383 ; gain = 495.531 ; free physical = 5791 ; free virtual = 41134 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 496.531 ; free physical = 5790 ; free virtual = 41133 Phase 2 Final Placement Cleanup Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.395 ; gain = 496.531 ; free physical = 5835 ; free virtual = 41181 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.383 ; gain = 495.531 ; free physical = 5837 ; free virtual = 41183 Starting Placer Task 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.383 ; gain = 575.562 ; free physical = 5853 ; free virtual = 41200 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1550.957 ; gain = 0.000 ; free physical = 5828 ; free virtual = 41176 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.395 ; gain = 496.531 ; free physical = 5812 ; free virtual = 41160 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 5808 ; free virtual = 41157 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.90 . Memory (MB): peak = 1550.957 ; gain = 0.000 ; free physical = 5775 ; free virtual = 41125 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.789 ; gain = 0.000 ; free physical = 5564 ; free virtual = 40930 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.789 ; gain = 0.000 ; free physical = 5465 ; free virtual = 40806 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 5156 ; free virtual = 40497 Phase 1 Build RT Design | Checksum: 972cf7e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.938 ; gain = 92.668 ; free physical = 5142 ; free virtual = 40483 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 972cf7e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.926 ; gain = 96.656 ; free physical = 5080 ; free virtual = 40421 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 972cf7e0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.926 ; gain = 96.656 ; free physical = 5080 ; free virtual = 40421 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.980 ; gain = 103.711 ; free physical = 5037 ; free virtual = 40378 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: 118b3be9c Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2134.082 ; gain = 49.668 ; free physical = 5013 ; free virtual = 40355 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4987 ; free virtual = 40328 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4977 ; free virtual = 40318 Phase 4 Rip-up And Reroute | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4978 ; free virtual = 40320 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4979 ; free virtual = 40320 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4980 ; free virtual = 40321 Phase 6 Post Hold Fix | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4980 ; free virtual = 40322 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 2.1 Fix Topology Constraints Phase 7 Route finalize | Checksum: 155c195dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 4976 ; free virtual = 40317 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 155c195dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 4975 ; free virtual = 40316 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 155c195dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 4974 ; free virtual = 40315 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 5006 ; free virtual = 40348 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2110.770 ; gain = 178.516 ; free physical = 5005 ; free virtual = 40346 Phase 2.1 Fix Topology Constraints | Checksum: 118b3be9c Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2144.070 ; gain = 59.656 ; free physical = 4994 ; free virtual = 40335 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 118b3be9c Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2144.070 ; gain = 59.656 ; free physical = 4990 ; free virtual = 40331 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 4964 ; free virtual = 40307 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 4884 ; free virtual = 40225 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4847 ; free virtual = 40188 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4869 ; free virtual = 40210 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Running DRC as a precondition to command write_bitstream Phase 4.1 Global Iteration 0 | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4863 ; free virtual = 40204 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4858 ; free virtual = 40200 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4854 ; free virtual = 40195 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4850 ; free virtual = 40191 Phase 6 Post Hold Fix | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4844 ; free virtual = 40186 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 145a2d7e1 Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4802 ; free virtual = 40143 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 145a2d7e1 Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4796 ; free virtual = 40138 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 145a2d7e1 Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4748 ; free virtual = 40090 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.375 ; gain = 93.961 ; free physical = 4793 ; free virtual = 40134 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 2217.164 ; gain = 164.766 ; free physical = 4793 ; free virtual = 40134 Writing placer database... Loading site data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Processing options... Creating bitmap... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 4462 ; free virtual = 39821 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 4416 ; free virtual = 39778 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 4422 ; free virtual = 39786 Phase 2 Global Placement Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.164 ; gain = 0.000 ; free physical = 4381 ; free virtual = 39751 Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2217.164 ; gain = 0.000 ; free physical = 4215 ; free virtual = 39559 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 4040 ; free virtual = 39385 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Loading site data... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 4063 ; free virtual = 39408 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: 15af38611 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.953 ; gain = 42.668 ; free physical = 3952 ; free virtual = 39297 Loading route data... Processing options... Creating bitmap... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3938 ; free virtual = 39283 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 3.3 Area Swap Optimization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15af38611 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 3910 ; free virtual = 39255 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15af38611 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2074.941 ; gain = 49.656 ; free physical = 3912 ; free virtual = 39256 Loading data files... Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3902 ; free virtual = 39247 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3934 ; free virtual = 39279 Phase 3.5 Small Shape Detail Placement Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10d853c8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.371 ; gain = 62.086 ; free physical = 3937 ; free virtual = 39282 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10d853c8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3938 ; free virtual = 39282 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10d853c8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3935 ; free virtual = 39279 Phase 4 Rip-up And Reroute | Checksum: 10d853c8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3937 ; free virtual = 39282 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3936 ; free virtual = 39281 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3936 ; free virtual = 39280 Phase 6 Post Hold Fix | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3936 ; free virtual = 39280 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2088.371 ; gain = 63.086 ; free physical = 3922 ; free virtual = 39267 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 3922 ; free virtual = 39267 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 3912 ; free virtual = 39257 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2091.371 ; gain = 66.086 ; free physical = 3950 ; free virtual = 39295 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2130.160 ; gain = 136.891 ; free physical = 3940 ; free virtual = 39285 Creating bitstream... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2130.160 ; gain = 0.000 ; free physical = 3900 ; free virtual = 39248 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3847 ; free virtual = 39195 Phase 3.6 Re-assign LUT pins INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3824 ; free virtual = 39169 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3793 ; free virtual = 39139 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3718 ; free virtual = 39064 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3708 ; free virtual = 39054 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3708 ; free virtual = 39054 Phase 4.3 Placer Reporting Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3533 ; free virtual = 38878 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3509 ; free virtual = 38855 INFO: [Timing 38-35] Done setting XDC timing constraints. Writing bitstream ./design.bit... Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3488 ; free virtual = 38833 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 3556 ; free virtual = 38905 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 3565 ; free virtual = 38914 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Vivado 12-1842] Bitgen Completed Successfully. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 3816 ; free virtual = 39166 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 15b0a291a Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 3757 ; free virtual = 39107 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15b0a291a Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 3689 ; free virtual = 39039 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15b0a291a Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 3689 ; free virtual = 39039 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 3653 ; free virtual = 39003 Phase 3 Initial Routing Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3676 ; free virtual = 39026 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3690 ; free virtual = 39040 Phase 4 Rip-up And Reroute | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3691 ; free virtual = 39041 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3692 ; free virtual = 39042 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3693 ; free virtual = 39043 Phase 6 Post Hold Fix | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3694 ; free virtual = 39044 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 3705 ; free virtual = 39057 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 3704 ; free virtual = 39056 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 115f91288 Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 3704 ; free virtual = 39056 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 3736 ; free virtual = 39089 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 3735 ; free virtual = 39087 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Writing placer database... Writing XDEF routing. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 3767 ; free virtual = 39122 Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.160 ; gain = 452.203 ; free physical = 3742 ; free virtual = 39096 Phase 1.3 Build Placer Netlist Model Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Running DRC as a precondition to command write_bitstream INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 3714 ; free virtual = 39068 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:14 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 2003.160 ; gain = 452.203 ; free physical = 4468 ; free virtual = 39821 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 2003.160 ; gain = 452.203 ; free physical = 4418 ; free virtual = 39772 Loading site data... Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:34 . Memory (MB): peak = 2003.160 ; gain = 452.203 ; free physical = 4390 ; free virtual = 39744 Phase 2 Global Placement INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:47 . Memory (MB): peak = 2607.281 ; gain = 387.621 ; free physical = 4379 ; free virtual = 39733 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:15 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Writing bitstream ./design.bit... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 5565 ; free virtual = 40924 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 5518 ; free virtual = 40876 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 5429 ; free virtual = 40787 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 5377 ; free virtual = 40735 Phase 3.4 Pipeline Register Optimization Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 2454.875 ; gain = 344.105 ; free physical = 5386 ; free virtual = 40744 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:22 2019... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 5392 ; free virtual = 40750 Phase 3.5 Small Shape Detail Placement Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_016/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_014 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6209 ; free virtual = 41568 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6193 ; free virtual = 41552 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6172 ; free virtual = 41531 Loading site data... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6162 ; free virtual = 41521 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Loading route data... Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:45 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6134 ; free virtual = 41493 Phase 4.2 Post Placement Cleanup Processing options... Creating bitmap... Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6124 ; free virtual = 41483 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:46 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6123 ; free virtual = 41482 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:47 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6114 ; free virtual = 41473 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:47 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6113 ; free virtual = 41473 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:47 . Memory (MB): peak = 2099.207 ; gain = 548.250 ; free physical = 6145 ; free virtual = 41504 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:49 . Memory (MB): peak = 2099.207 ; gain = 631.953 ; free physical = 6141 ; free virtual = 41500 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:57 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 6137 ; free virtual = 41500 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:57 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 6103 ; free virtual = 41466 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:57 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 6127 ; free virtual = 41490 Writing bitstream ./design.bit... Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12bd49b1d Time (s): cpu = 00:00:41 ; elapsed = 00:00:57 . Memory (MB): peak = 2087.375 ; gain = 62.086 ; free physical = 6370 ; free virtual = 41738 Phase 3 Initial Routing INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6434 ; free virtual = 41801 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6431 ; free virtual = 41799 Phase 4 Rip-up And Reroute | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6431 ; free virtual = 41799 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6431 ; free virtual = 41799 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6431 ; free virtual = 41798 Phase 6 Post Hold Fix | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6431 ; free virtual = 41798 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:58 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 6403 ; free virtual = 41770 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:58 . Memory (MB): peak = 2091.375 ; gain = 66.086 ; free physical = 6403 ; free virtual = 41770 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:58 . Memory (MB): peak = 2091.375 ; gain = 66.086 ; free physical = 6424 ; free virtual = 41792 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:58 . Memory (MB): peak = 2091.375 ; gain = 66.086 ; free physical = 6463 ; free virtual = 41830 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:01:00 . Memory (MB): peak = 2130.164 ; gain = 136.891 ; free physical = 6463 ; free virtual = 41830 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 6411 ; free virtual = 41781 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Phase 1 Build RT Design | Checksum: 16930dc89 Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2133.078 ; gain = 48.668 ; free physical = 6338 ; free virtual = 41706 Phase 1 Build RT Design | Checksum: fa6cad5b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2134.066 ; gain = 49.668 ; free physical = 6339 ; free virtual = 41707 Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:55 . Memory (MB): peak = 2608.949 ; gain = 390.160 ; free physical = 6364 ; free virtual = 41736 Phase 2.1 Fix Topology Constraints INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:41 2019... Phase 2.1 Fix Topology Constraints | Checksum: 16930dc89 Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 6385 ; free virtual = 41755 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 16930dc89 Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 6393 ; free virtual = 41764 Phase 2.1 Fix Topology Constraints | Checksum: fa6cad5b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2143.594 ; gain = 59.195 ; free physical = 6397 ; free virtual = 41767 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: fa6cad5b Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2143.594 ; gain = 59.195 ; free physical = 6405 ; free virtual = 41775 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2469.266 ; gain = 339.105 ; free physical = 7604 ; free virtual = 42974 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:42 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:57 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 7620 ; free virtual = 42991 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 19ba50c22 Time (s): cpu = 00:00:43 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 7643 ; free virtual = 43014 Phase 3 Initial Routing touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8492 ; free virtual = 43865 Phase 3 Initial Routing | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8492 ; free virtual = 43864 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8470 ; free virtual = 43843 Phase 4.1 Global Iteration 0 | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8469 ; free virtual = 43841 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 4 Rip-up And Reroute | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8522 ; free virtual = 43895 Phase 5 Delay and Skew Optimization Phase 4 Rip-up And Reroute | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8522 ; free virtual = 43894 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8515 ; free virtual = 43887 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 5 Delay and Skew Optimization | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8515 ; free virtual = 43887 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8505 ; free virtual = 43877 Phase 6.1 Hold Fix Iter | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8504 ; free virtual = 43876 Phase 6 Post Hold Fix | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:57 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8487 ; free virtual = 43859 Phase 6 Post Hold Fix | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:58 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8481 ; free virtual = 43853 Phase 7 Route finalize Phase 7 Route finalize Writing bitstream ./design.bit... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8443 ; free virtual = 43819 Phase 8 Verifying routed nets Verification completed successfully Phase 7 Route finalize | Checksum: 1065a9434 Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8433 ; free virtual = 43809 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8415 ; free virtual = 43791 Phase 9 Depositing Routes Phase 8 Verifying routed nets | Checksum: 1065a9434 Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8407 ; free virtual = 43783 Phase 9 Depositing Routes touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 Phase 9 Depositing Routes | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8778 ; free virtual = 44160 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2197.523 ; gain = 113.125 ; free physical = 8827 ; free virtual = 44209 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:01:02 . Memory (MB): peak = 2236.312 ; gain = 183.930 ; free physical = 8828 ; free virtual = 44210 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 9 Depositing Routes | Checksum: 1065a9434 Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8830 ; free virtual = 44212 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:58 . Memory (MB): peak = 2178.871 ; gain = 94.461 ; free physical = 8877 ; free virtual = 44259 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:01:01 . Memory (MB): peak = 2217.660 ; gain = 165.266 ; free physical = 8874 ; free virtual = 44255 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing placer database... Writing placer database... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13533 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2453.867 ; gain = 343.105 ; free physical = 8780 ; free virtual = 44183 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:45 2019... Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13611 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:35:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:46 . Memory (MB): peak = 2606.324 ; gain = 389.160 ; free physical = 9571 ; free virtual = 44995 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:35:47 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2236.312 ; gain = 0.000 ; free physical = 10638 ; free virtual = 46071 Writing XDEF routing. Bitstream size: 4243411 bytes Writing XDEF routing logical nets. Writing XDEF routing special nets. Config size: 1060815 words Number of configuration frames: 9996 DONE Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.660 ; gain = 0.000 ; free physical = 10644 ; free virtual = 46088 touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13782 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10284 ; free virtual = 45678 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10236 ; free virtual = 45631 --------------------------------------------------------------------------------- Loading site data... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6804] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6970] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9956 ; free virtual = 45351 --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10022 ; free virtual = 45417 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10041 ; free virtual = 45436 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10068 ; free virtual = 45463 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9869 ; free virtual = 45264 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9961 ; free virtual = 45356 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9969 ; free virtual = 45364 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9904 ; free virtual = 45300 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2130.426 ; gain = 31.227 ; free physical = 9671 ; free virtual = 45066 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2136.414 ; gain = 37.215 ; free physical = 9555 ; free virtual = 44950 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2136.414 ; gain = 37.215 ; free physical = 9554 ; free virtual = 44949 Loading data files... Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9518 ; free virtual = 44913 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9458 ; free virtual = 44853 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9449 ; free virtual = 44845 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9448 ; free virtual = 44844 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9448 ; free virtual = 44844 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9448 ; free virtual = 44844 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9448 ; free virtual = 44844 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9480 ; free virtual = 44876 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9478 ; free virtual = 44874 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9473 ; free virtual = 44869 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9501 ; free virtual = 44897 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:53 . Memory (MB): peak = 2193.258 ; gain = 94.059 ; free physical = 9495 ; free virtual = 44890 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 9482 ; free virtual = 44878 --------------------------------------------------------------------------------- Writing placer database... Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9006 ; free virtual = 44422 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 8999 ; free virtual = 44416 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 8993 ; free virtual = 44411 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8992 ; free virtual = 44410 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.570 ; gain = 216.121 ; free physical = 9255 ; free virtual = 44656 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9148 ; free virtual = 44550 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9150 ; free virtual = 44551 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9163 ; free virtual = 44565 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9161 ; free virtual = 44563 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9156 ; free virtual = 44557 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9153 ; free virtual = 44554 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9151 ; free virtual = 44552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.570 ; gain = 216.121 ; free physical = 9150 ; free virtual = 44551 Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9135 ; free virtual = 44536 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9138 ; free virtual = 44539 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13866 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9139 ; free virtual = 44540 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13886 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:16] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9089 ; free virtual = 44490 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9084 ; free virtual = 44485 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9071 ; free virtual = 44472 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9066 ; free virtual = 44467 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9062 ; free virtual = 44463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9060 ; free virtual = 44461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9059 ; free virtual = 44460 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.555 ; gain = 225.105 ; free physical = 9054 ; free virtual = 44455 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.562 ; gain = 225.105 ; free physical = 9055 ; free virtual = 44456 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9062 ; free virtual = 44464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9046 ; free virtual = 44448 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 9046 ; free virtual = 44448 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:36:10 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 2469.270 ; gain = 339.105 ; free physical = 8775 ; free virtual = 44177 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:36:10 2019... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13969 Loading site data... Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: Launching helper process for spawning children vivado processes DONE INFO: Helper process launched with PID 13994 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading route data... 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9627 ; free virtual = 45029 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Processing options... Creating bitmap... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Processing options... Creating bitmap... touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_016 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 9464 ; free virtual = 44867 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 9421 ; free virtual = 44824 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 9421 ; free virtual = 44824 Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1416.594 ; gain = 333.703 ; free physical = 9302 ; free virtual = 44706 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.625 ; gain = 0.000 ; free physical = 9201 ; free virtual = 44605 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1482.625 ; gain = 0.000 ; free physical = 9200 ; free virtual = 44604 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2129.637 ; gain = 30.430 ; free physical = 9135 ; free virtual = 44539 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2136.625 ; gain = 37.418 ; free physical = 9089 ; free virtual = 44493 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2136.625 ; gain = 37.418 ; free physical = 9089 ; free virtual = 44493 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9074 ; free virtual = 44478 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9056 ; free virtual = 44460 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 9018 ; free virtual = 44422 Phase 3 Initial Routing No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8971 ; free virtual = 44376 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8966 ; free virtual = 44370 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8966 ; free virtual = 44370 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8966 ; free virtual = 44370 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8966 ; free virtual = 44370 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8966 ; free virtual = 44370 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8941 ; free virtual = 44345 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8939 ; free virtual = 44344 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8938 ; free virtual = 44342 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2156.680 ; gain = 57.473 ; free physical = 8973 ; free virtual = 44377 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2195.469 ; gain = 96.262 ; free physical = 8972 ; free virtual = 44376 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8971 ; free virtual = 44376 --------------------------------------------------------------------------------- Writing placer database... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8929 ; free virtual = 44335 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 8934 ; free virtual = 44345 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 8932 ; free virtual = 44344 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 8931 ; free virtual = 44344 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8927 ; free virtual = 44340 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:18 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 8915 ; free virtual = 44329 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 8877 ; free virtual = 44291 --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8771 ; free virtual = 44192 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8767 ; free virtual = 44188 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8757 ; free virtual = 44179 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8758 ; free virtual = 44179 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8757 ; free virtual = 44179 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8757 ; free virtual = 44179 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8756 ; free virtual = 44179 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8758 ; free virtual = 44180 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 8759 ; free virtual = 44182 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2195.469 ; gain = 0.000 ; free physical = 8671 ; free virtual = 44099 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:16 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 8666 ; free virtual = 44093 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2] Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:21 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8851 ; free virtual = 44266 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8757 ; free virtual = 44171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 8752 ; free virtual = 44167 --------------------------------------------------------------------------------- No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 8747 ; free virtual = 44162 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 8734 ; free virtual = 44149 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 8751 ; free virtual = 44166 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:36:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading data files... Writing bitstream ./design.bit... 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2605.781 ; gain = 388.121 ; free physical = 8758 ; free virtual = 44173 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:36:34 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:36:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9718 ; free virtual = 45135 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9835 ; free virtual = 45252 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9949 ; free virtual = 45367 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9964 ; free virtual = 45381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9980 ; free virtual = 45397 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9990 ; free virtual = 45407 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10009 ; free virtual = 45426 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:46 . Memory (MB): peak = 2608.934 ; gain = 372.621 ; free physical = 10013 ; free virtual = 45430 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:36:34 2019... Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10058 ; free virtual = 45474 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10087 ; free virtual = 45503 Bitstream size: 4243411 bytes INFO: [Project 1-571] Translating synthesized netlist Config size: 1060815 words Number of configuration frames: 9996 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_016/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 INFO: [Project 1-570] Preparing netlist for logic optimization touch build/specimen_015/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_017 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 10887 ; free virtual = 46310 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 10687 ; free virtual = 46112 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:45 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 10640 ; free virtual = 46064 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:36:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2531.363 ; gain = 338.105 ; free physical = 10533 ; free virtual = 45958 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:36:37 2019... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2] INFO: [Timing 38-35] Done setting XDC timing constraints. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 11477 ; free virtual = 46901 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 11474 ; free virtual = 46899 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 11473 ; free virtual = 46898 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 11474 ; free virtual = 46899 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 11473 ; free virtual = 46899 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 11469 ; free virtual = 46895 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 11469 ; free virtual = 46895 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.113 ; gain = 0.000 ; free physical = 11459 ; free virtual = 46887 touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Placer Task INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.156 ; gain = 511.531 ; free physical = 11456 ; free virtual = 46896 Phase 1.3 Build Placer Netlist Model Phase 1 Placer Initialization 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 11447 ; free virtual = 46889 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 11434 ; free virtual = 46878 Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.156 ; gain = 511.531 ; free physical = 11434 ; free virtual = 46878 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.156 ; gain = 511.531 ; free physical = 11426 ; free virtual = 46871 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.156 ; gain = 511.531 ; free physical = 11423 ; free virtual = 46868 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.156 ; gain = 511.531 ; free physical = 11420 ; free virtual = 46864 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.156 ; gain = 511.531 ; free physical = 11423 ; free virtual = 46867 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.156 ; gain = 577.562 ; free physical = 11424 ; free virtual = 46869 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 11407 ; free virtual = 46852 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11396 ; free virtual = 46822 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.715 ; gain = 0.000 ; free physical = 11390 ; free virtual = 46836 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1461.715 ; gain = 0.000 ; free physical = 11390 ; free virtual = 46835 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:34 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11282 ; free virtual = 46708 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:34 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11281 ; free virtual = 46707 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2] INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14492 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 11345 ; free virtual = 46772 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 11321 ; free virtual = 46755 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11223 ; free virtual = 46670 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11220 ; free virtual = 46648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11190 ; free virtual = 46638 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11184 ; free virtual = 46632 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11167 ; free virtual = 46615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11164 ; free virtual = 46611 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11160 ; free virtual = 46607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11156 ; free virtual = 46603 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11154 ; free virtual = 46602 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 11148 ; free virtual = 46596 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 11148 ; free virtual = 46596 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11095 ; free virtual = 46523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11094 ; free virtual = 46522 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 10899 ; free virtual = 46327 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1343.102 ; gain = 247.184 ; free physical = 10395 ; free virtual = 45824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 1348.070 ; gain = 252.152 ; free physical = 10404 ; free virtual = 45835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1343.102 ; gain = 247.184 ; free physical = 10494 ; free virtual = 45926 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10523 ; free virtual = 45955 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:46 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10591 ; free virtual = 46023 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] No constraint files found. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1356.102 ; gain = 260.184 ; free physical = 10541 ; free virtual = 45973 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:44 . Memory (MB): peak = 1356.102 ; gain = 260.184 ; free physical = 10527 ; free virtual = 45959 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10513 ; free virtual = 45945 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10509 ; free virtual = 45941 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:36:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10495 ; free virtual = 45927 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2533.574 ; gain = 338.105 ; free physical = 10492 ; free virtual = 45924 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:36:55 2019... --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10491 ; free virtual = 45923 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10496 ; free virtual = 45927 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10498 ; free virtual = 45930 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10496 ; free virtual = 45928 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 10497 ; free virtual = 45929 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1351.086 ; gain = 255.160 ; free physical = 10506 ; free virtual = 45938 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11426 ; free virtual = 46858 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 11548 ; free virtual = 46980 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- touch build/specimen_013/OK Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_018 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:16] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11341 ; free virtual = 46773 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:46 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11333 ; free virtual = 46765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:7] --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11331 ; free virtual = 46764 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 1 Placer Initialization INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11367 ; free virtual = 46800 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 11359 ; free virtual = 46792 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11360 ; free virtual = 46793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11363 ; free virtual = 46796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11364 ; free virtual = 46797 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.078 ; gain = 268.160 ; free physical = 11366 ; free virtual = 46799 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1364.086 ; gain = 268.160 ; free physical = 11368 ; free virtual = 46801 INFO: [Project 1-571] Translating synthesized netlist Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 11376 ; free virtual = 46811 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11261 ; free virtual = 46694 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11092 ; free virtual = 46526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 11091 ; free virtual = 46525 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl INFO: [Device 21-403] Loading part xc7z020clg400-1 # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14684 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 10922 ; free virtual = 46356 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14725 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 10615 ; free virtual = 46049 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14780 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 10558 ; free virtual = 45992 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10559 ; free virtual = 45992 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 10544 ; free virtual = 45977 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 10542 ; free virtual = 45976 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 10541 ; free virtual = 45975 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 10541 ; free virtual = 45975 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 10541 ; free virtual = 45975 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 10544 ; free virtual = 45978 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 10544 ; free virtual = 45978 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 10298 ; free virtual = 45732 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 10276 ; free virtual = 45709 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 10257 ; free virtual = 45690 Phase 2 Global Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 10260 ; free virtual = 45693 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 10244 ; free virtual = 45678 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10166 ; free virtual = 45600 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 10084 ; free virtual = 45518 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 10061 ; free virtual = 45494 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10055 ; free virtual = 45489 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10048 ; free virtual = 45482 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10038 ; free virtual = 45472 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10038 ; free virtual = 45472 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 10038 ; free virtual = 45472 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10038 ; free virtual = 45472 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10037 ; free virtual = 45471 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10037 ; free virtual = 45471 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 10038 ; free virtual = 45472 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 10040 ; free virtual = 45474 INFO: [Project 1-571] Translating synthesized netlist Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 10029 ; free virtual = 45463 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 10012 ; free virtual = 45446 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 10001 ; free virtual = 45435 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9924 ; free virtual = 45357 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 9917 ; free virtual = 45351 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9716 ; free virtual = 45150 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9693 ; free virtual = 45127 Phase 3.7 Pipeline Register Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9685 ; free virtual = 45119 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9710 ; free virtual = 45144 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9723 ; free virtual = 45157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 9721 ; free virtual = 45155 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9721 ; free virtual = 45155 --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9720 ; free virtual = 45154 Phase 4.2 Post Placement Cleanup INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 9717 ; free virtual = 45152 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9704 ; free virtual = 45138 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9678 ; free virtual = 45113 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9661 ; free virtual = 45095 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9647 ; free virtual = 45081 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 9632 ; free virtual = 45067 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 9632 ; free virtual = 45066 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9333 ; free virtual = 44768 --------------------------------------------------------------------------------- Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9170 ; free virtual = 44604 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9170 ; free virtual = 44604 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 9142 ; free virtual = 44577 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 9135 ; free virtual = 44570 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 8953 ; free virtual = 44387 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15612 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 8991 ; free virtual = 44426 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 8980 ; free virtual = 44415 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.867 ; gain = 0.000 ; free physical = 8958 ; free virtual = 44393 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.59 . Memory (MB): peak = 1554.867 ; gain = 0.000 ; free physical = 8991 ; free virtual = 44426 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 9000 ; free virtual = 44434 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 9021 ; free virtual = 44456 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 9022 ; free virtual = 44457 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 9021 ; free virtual = 44456 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 9023 ; free virtual = 44458 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.36 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 9018 ; free virtual = 44452 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2058.934 ; gain = 94.668 ; free physical = 9021 ; free virtual = 44456 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 8992 ; free virtual = 44427 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 8993 ; free virtual = 44428 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8960 ; free virtual = 44395 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8971 ; free virtual = 44406 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8971 ; free virtual = 44406 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8973 ; free virtual = 44408 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8975 ; free virtual = 44410 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8974 ; free virtual = 44409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8974 ; free virtual = 44409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8973 ; free virtual = 44408 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 8972 ; free virtual = 44407 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 8971 ; free virtual = 44406 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8976 ; free virtual = 44411 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8982 ; free virtual = 44417 Phase 4 Rip-up And Reroute | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8982 ; free virtual = 44417 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8983 ; free virtual = 44418 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8983 ; free virtual = 44418 Phase 6 Post Hold Fix | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 8983 ; free virtual = 44418 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 9028 ; free virtual = 44463 Phase 1.4 Constrain Clocks/Macros Phase 7 Route finalize | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 9028 ; free virtual = 44463 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 9029 ; free virtual = 44464 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 9033 ; free virtual = 44468 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 9071 ; free virtual = 44506 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 9073 ; free virtual = 44508 Phase 1 Build RT Design | Checksum: 18806395d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.840 ; gain = 41.668 ; free physical = 9117 ; free virtual = 44553 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 9109 ; free virtual = 44547 Writing placer database... Writing XDEF routing. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18806395d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.828 ; gain = 47.656 ; free physical = 9087 ; free virtual = 44527 Phase 2.2 Pre Route Cleanup Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 9086 ; free virtual = 44526 Phase 2.2 Pre Route Cleanup | Checksum: 18806395d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.828 ; gain = 47.656 ; free physical = 9084 ; free virtual = 44525 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 9069 ; free virtual = 44511 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-570] Preparing netlist for logic optimization Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: df19d8a1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.133 ; gain = 59.961 ; free physical = 9146 ; free virtual = 44601 Phase 3 Initial Routing Phase 1 Placer Initialization Running DRC as a precondition to command write_bitstream Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1554.859 ; gain = 0.000 ; free physical = 9174 ; free virtual = 44630 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9180 ; free virtual = 44636 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.70 . Memory (MB): peak = 1554.859 ; gain = 0.000 ; free physical = 9184 ; free virtual = 44641 Phase 4.1 Global Iteration 0 | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9185 ; free virtual = 44641 Phase 4 Rip-up And Reroute | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9188 ; free virtual = 44644 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9190 ; free virtual = 44646 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9215 ; free virtual = 44652 --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9215 ; free virtual = 44651 Phase 6 Post Hold Fix | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9214 ; free virtual = 44651 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.133 ; gain = 62.961 ; free physical = 9296 ; free virtual = 44732 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: df19d8a1 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.133 ; gain = 64.961 ; free physical = 9304 ; free virtual = 44741 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: df19d8a1 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.133 ; gain = 64.961 ; free physical = 9330 ; free virtual = 44771 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.133 ; gain = 64.961 ; free physical = 9366 ; free virtual = 44811 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2129.922 ; gain = 135.766 ; free physical = 9365 ; free virtual = 44812 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.49 . Memory (MB): peak = 2129.922 ; gain = 0.000 ; free physical = 9447 ; free virtual = 44907 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9493 ; free virtual = 44950 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9520 ; free virtual = 44958 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9529 ; free virtual = 44967 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9541 ; free virtual = 44979 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 9676 ; free virtual = 45113 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 9697 ; free virtual = 45135 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9730 ; free virtual = 45168 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 9826 ; free virtual = 45264 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 9901 ; free virtual = 45338 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.3 Area Swap Optimization Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 9974 ; free virtual = 45411 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 9974 ; free virtual = 45412 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10001 ; free virtual = 45439 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10040 ; free virtual = 45477 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10109 ; free virtual = 45546 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10108 ; free virtual = 45546 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10154 ; free virtual = 45591 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10156 ; free virtual = 45594 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10163 ; free virtual = 45601 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10163 ; free virtual = 45601 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10163 ; free virtual = 45601 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10163 ; free virtual = 45600 Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 10179 ; free virtual = 45617 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10194 ; free virtual = 45631 --------------------------------------------------------------------------------- Loading data files... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10475 ; free virtual = 45913 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10488 ; free virtual = 45926 Phase 3.7 Pipeline Register Optimization INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10526 ; free virtual = 45964 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10623 ; free virtual = 46060 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10738 ; free virtual = 46175 Phase 4.2 Post Placement Cleanup INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10663 ; free virtual = 46100 Phase 4.3 Placer Reporting Loading data files... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10636 ; free virtual = 46074 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10609 ; free virtual = 46046 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1336.066 ; gain = 240.152 ; free physical = 10609 ; free virtual = 46046 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10594 ; free virtual = 46032 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 543.246 ; free physical = 10574 ; free virtual = 46012 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 623.949 ; free physical = 10573 ; free virtual = 46011 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:16] Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1347.098 ; gain = 251.184 ; free physical = 10301 ; free virtual = 45739 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10325 ; free virtual = 45763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1347.098 ; gain = 251.184 ; free physical = 10325 ; free virtual = 45763 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 10281 ; free virtual = 45720 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 10290 ; free virtual = 45729 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 10216 ; free virtual = 45654 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9920 ; free virtual = 45359 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9900 ; free virtual = 45338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9837 ; free virtual = 45276 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9815 ; free virtual = 45254 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9776 ; free virtual = 45215 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 9801 ; free virtual = 45240 --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9801 ; free virtual = 45240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9800 ; free virtual = 45239 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.074 ; gain = 259.160 ; free physical = 9818 ; free virtual = 45257 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.082 ; gain = 259.160 ; free physical = 9828 ; free virtual = 45267 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 9841 ; free virtual = 45280 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 9243 ; free virtual = 44682 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 9213 ; free virtual = 44653 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading site data... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 9118 ; free virtual = 44557 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.441 ; gain = 0.000 ; free physical = 9088 ; free virtual = 44527 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 10ee63a33 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2057.930 ; gain = 93.668 ; free physical = 8898 ; free virtual = 44338 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10ee63a33 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 8858 ; free virtual = 44297 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10ee63a33 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 8858 ; free virtual = 44297 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8816 ; free virtual = 44257 Phase 3 Initial Routing WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8832 ; free virtual = 44275 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8846 ; free virtual = 44289 Phase 4 Rip-up And Reroute | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8847 ; free virtual = 44290 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8850 ; free virtual = 44293 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8850 ; free virtual = 44294 Phase 6 Post Hold Fix | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8851 ; free virtual = 44294 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.156 ; gain = 456.203 ; free physical = 8851 ; free virtual = 44294 Phase 1.3 Build Placer Netlist Model Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 7 Route finalize | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 9065 ; free virtual = 44509 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 9063 ; free virtual = 44506 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 9060 ; free virtual = 44503 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 9090 ; free virtual = 44533 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 9092 ; free virtual = 44535 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 9082 ; free virtual = 44527 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 8990 ; free virtual = 44433 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 9007 ; free virtual = 44451 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8878 ; free virtual = 44321 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Running DRC as a precondition to command write_bitstream --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8766 ; free virtual = 44210 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:37:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.871 ; gain = 342.105 ; free physical = 8503 ; free virtual = 43947 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:37:50 2019... Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 8505 ; free virtual = 43949 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8516 ; free virtual = 43960 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8516 ; free virtual = 43960 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8571 ; free virtual = 44015 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8580 ; free virtual = 44024 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8603 ; free virtual = 44047 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8615 ; free virtual = 44059 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8677 ; free virtual = 44121 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 9027 ; free virtual = 44471 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 9225 ; free virtual = 44669 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. Bitstream size: 4243411 bytes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 9414 ; free virtual = 44858 Config size: 1060815 words Number of configuration frames: 9996 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device DONE Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.156 ; gain = 456.203 ; free physical = 9404 ; free virtual = 44848 Phase 1.4 Constrain Clocks/Macros touch build/specimen_018/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_019 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.156 ; gain = 456.203 ; free physical = 9368 ; free virtual = 44812 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2004.156 ; gain = 456.203 ; free physical = 9360 ; free virtual = 44804 Phase 2 Global Placement INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9276 ; free virtual = 44720 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9274 ; free virtual = 44719 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9274 ; free virtual = 44718 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9280 ; free virtual = 44725 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9280 ; free virtual = 44725 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9318 ; free virtual = 44763 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 9321 ; free virtual = 44766 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 9270 ; free virtual = 44716 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 9227 ; free virtual = 44673 Phase 1.4 Constrain Clocks/Macros INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 9229 ; free virtual = 44674 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 9207 ; free virtual = 44652 Phase 2 Final Placement Cleanup WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 9150 ; free virtual = 44595 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Loading data files... Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 9187 ; free virtual = 44632 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 9185 ; free virtual = 44631 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9092 ; free virtual = 44537 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9067 ; free virtual = 44512 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9040 ; free virtual = 44485 Phase 3.3 Area Swap Optimization Writing bitstream ./design.bit... Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 8994 ; free virtual = 44441 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 8982 ; free virtual = 44432 Phase 3.5 Small Shape Detail Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 9091 ; free virtual = 44540 Phase 1.4 Constrain Clocks/Macros Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 9251 ; free virtual = 44701 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 9230 ; free virtual = 44680 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 9217 ; free virtual = 44667 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 9206 ; free virtual = 44656 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 9204 ; free virtual = 44653 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9125 ; free virtual = 44575 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9112 ; free virtual = 44562 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9121 ; free virtual = 44571 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9128 ; free virtual = 44578 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9111 ; free virtual = 44561 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9102 ; free virtual = 44551 Phase 4.3 Placer Reporting report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9090 ; free virtual = 44539 Phase 4.4 Final Placement Cleanup Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9035 ; free virtual = 44485 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 8997 ; free virtual = 44447 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:38:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2469.027 ; gain = 339.105 ; free physical = 9034 ; free virtual = 44484 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:38:01 2019... Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2108.207 ; gain = 560.254 ; free physical = 9040 ; free virtual = 44490 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2108.207 ; gain = 640.957 ; free physical = 9040 ; free virtual = 44489 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.961 ; gain = 31.758 ; free physical = 9095 ; free virtual = 44545 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 9072 ; free virtual = 44522 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 9072 ; free virtual = 44522 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 9872 ; free virtual = 45323 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9862 ; free virtual = 45313 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9843 ; free virtual = 45294 touch build/specimen_015/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9842 ; free virtual = 45293 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9841 ; free virtual = 45293 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9841 ; free virtual = 45293 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9841 ; free virtual = 45293 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9841 ; free virtual = 45293 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9805 ; free virtual = 45256 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9803 ; free virtual = 45254 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9800 ; free virtual = 45251 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 9834 ; free virtual = 45285 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2193.793 ; gain = 94.590 ; free physical = 9832 ; free virtual = 45283 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Writing placer database... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 15 #of bits: 43412 #of tags: 700 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_020 Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1549.961 ; gain = 0.000 ; free physical = 9736 ; free virtual = 45191 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1549.961 ; gain = 0.000 ; free physical = 9697 ; free virtual = 45155 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 9262 ; free virtual = 44734 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 9277 ; free virtual = 44753 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 9270 ; free virtual = 44746 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1552.855 ; gain = 0.000 ; free physical = 9241 ; free virtual = 44699 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 9261 ; free virtual = 44719 Phase 1.3 Build Placer Netlist Model INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.87 . Memory (MB): peak = 1552.855 ; gain = 0.000 ; free physical = 9356 ; free virtual = 44815 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:38:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2455.867 ; gain = 345.105 ; free physical = 9187 ; free virtual = 44646 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:38:14 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 9206 ; free virtual = 44665 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 9892 ; free virtual = 45351 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 10074 ; free virtual = 45533 Phase 2 Global Placement touch build/specimen_019/OK ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18275 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9747 ; free virtual = 45211 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9726 ; free virtual = 45190 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9655 ; free virtual = 45119 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9672 ; free virtual = 45136 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9642 ; free virtual = 45106 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9528 ; free virtual = 44992 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9521 ; free virtual = 44986 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9511 ; free virtual = 44975 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9489 ; free virtual = 44953 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2130.426 ; gain = 39.230 ; free physical = 9480 ; free virtual = 44945 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.414 ; gain = 45.219 ; free physical = 9441 ; free virtual = 44906 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.414 ; gain = 45.219 ; free physical = 9441 ; free virtual = 44906 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9432 ; free virtual = 44897 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9416 ; free virtual = 44881 Phase 4.3 Placer Reporting Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9405 ; free virtual = 44870 Phase 3 Initial Routing Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9397 ; free virtual = 44861 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9390 ; free virtual = 44854 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9379 ; free virtual = 44844 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9373 ; free virtual = 44838 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9373 ; free virtual = 44838 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9373 ; free virtual = 44838 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9373 ; free virtual = 44838 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9373 ; free virtual = 44838 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9373 ; free virtual = 44838 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9387 ; free virtual = 44852 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9385 ; free virtual = 44850 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9367 ; free virtual = 44832 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9367 ; free virtual = 44832 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 630.953 ; free physical = 9376 ; free virtual = 44841 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.469 ; gain = 65.273 ; free physical = 9392 ; free virtual = 44857 Routing Is Done. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2195.258 ; gain = 104.062 ; free physical = 9378 ; free virtual = 44843 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 8968 ; free virtual = 44448 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 8863 ; free virtual = 44344 --------------------------------------------------------------------------------- Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2195.258 ; gain = 0.000 ; free physical = 8719 ; free virtual = 44207 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2004.164 ; gain = 454.203 ; free physical = 8591 ; free virtual = 44080 Phase 1.3 Build Placer Netlist Model WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18462 Running DRC as a precondition to command write_bitstream INFO: [Timing 38-35] Done setting XDC timing constraints. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Creating bitstream... Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 8324 ; free virtual = 43791 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.164 ; gain = 454.203 ; free physical = 8305 ; free virtual = 43776 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2004.164 ; gain = 454.203 ; free physical = 8296 ; free virtual = 43770 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8299 ; free virtual = 43766 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.164 ; gain = 454.203 ; free physical = 8298 ; free virtual = 43765 Phase 2 Global Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.387 ; gain = 499.531 ; free physical = 8255 ; free virtual = 43729 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8230 ; free virtual = 43698 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 8233 ; free virtual = 43701 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 8211 ; free virtual = 43683 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8196 ; free virtual = 43667 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8183 ; free virtual = 43655 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8140 ; free virtual = 43612 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8111 ; free virtual = 43583 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8082 ; free virtual = 43554 Phase 3.5 Small Shape Detail Placement INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:38:38 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.898 ; gain = 339.105 ; free physical = 8098 ; free virtual = 43570 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:38:38 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 499.531 ; free physical = 8105 ; free virtual = 43577 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 499.531 ; free physical = 8167 ; free virtual = 43638 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 499.531 ; free physical = 9119 ; free virtual = 44591 Phase 2 Final Placement Cleanup Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 499.531 ; free physical = 9095 ; free virtual = 44567 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed touch build/specimen_014/OK Phase 1 Build RT Design | Checksum: 13e11bf6c Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 9105 ; free virtual = 44577 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: Launching helper process for spawning children vivado processes Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13e11bf6c Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 9107 ; free virtual = 44579 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13e11bf6c Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 9106 ; free virtual = 44578 INFO: Helper process launched with PID 19270 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.387 ; gain = 499.531 ; free physical = 9100 ; free virtual = 44572 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 9098 ; free virtual = 44569 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9096 ; free virtual = 44568 --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4599df1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9063 ; free virtual = 44535 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b4599df1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9007 ; free virtual = 44479 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8991 ; free virtual = 44463 Phase 3.6 Re-assign LUT pins Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8988 ; free virtual = 44460 Phase 4 Rip-up And Reroute | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8988 ; free virtual = 44460 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8988 ; free virtual = 44460 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8989 ; free virtual = 44460 Phase 6 Post Hold Fix | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 8983 ; free virtual = 44455 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 8945 ; free virtual = 44417 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 8944 ; free virtual = 44416 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 8943 ; free virtual = 44414 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 8997 ; free virtual = 44469 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2111.762 ; gain = 179.516 ; free physical = 8996 ; free virtual = 44468 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8984 ; free virtual = 44456 Phase 3.7 Pipeline Register Optimization Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2111.762 ; gain = 0.000 ; free physical = 8983 ; free virtual = 44456 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8978 ; free virtual = 44451 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8941 ; free virtual = 44413 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8915 ; free virtual = 44387 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8934 ; free virtual = 44406 Phase 4.3 Placer Reporting Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] Running DRC as a precondition to command write_bitstream WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] Phase 4.3 Placer Reporting | Checksum: 181723f81 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8956 ; free virtual = 44428 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] Phase 4.4 Final Placement Cleanup WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8946 ; free virtual = 44418 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8913 ; free virtual = 44386 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design | Checksum: 169ce22cd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.082 ; gain = 50.668 ; free physical = 8933 ; free virtual = 44405 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8931 ; free virtual = 44403 --------------------------------------------------------------------------------- Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.211 ; gain = 550.250 ; free physical = 8928 ; free virtual = 44400 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2100.211 ; gain = 632.953 ; free physical = 8927 ; free virtual = 44399 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 8925 ; free virtual = 44397 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 169ce22cd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.070 ; gain = 59.656 ; free physical = 8836 ; free virtual = 44309 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 169ce22cd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.070 ; gain = 59.656 ; free physical = 8823 ; free virtual = 44296 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8801 ; free virtual = 44274 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 178199bf5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8723 ; free virtual = 44196 Phase 3 Initial Routing WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8781 ; free virtual = 44253 --------------------------------------------------------------------------------- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8785 ; free virtual = 44258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8780 ; free virtual = 44253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8780 ; free virtual = 44253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes Number of Nodes with overlaps = --------------------------------------------------------------------------------- 0 --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8779 ; free virtual = 44251 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8777 ; free virtual = 44249 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8775 ; free virtual = 44248 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Phase 3 Initial Routing | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8779 ; free virtual = 44251 Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 8772 ; free virtual = 44244 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 8773 ; free virtual = 44246 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8756 ; free virtual = 44228 INFO: [Project 1-571] Translating synthesized netlist Phase 4 Rip-up And Reroute | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8743 ; free virtual = 44216 Phase 5 Delay and Skew Optimization Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 5 Delay and Skew Optimization | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8737 ; free virtual = 44209 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 1 Build RT Design Phase 6.1 Hold Fix Iter | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8730 ; free virtual = 44202 Phase 6 Post Hold Fix | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8720 ; free virtual = 44192 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8689 ; free virtual = 44161 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8687 ; free virtual = 44159 Phase 9 Depositing Routes WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:16] Phase 1 Build RT Design | Checksum: 1a0edab69 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 8628 ; free virtual = 44101 Phase 9 Depositing Routes | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8622 ; free virtual = 44094 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 8662 ; free virtual = 44135 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 2218.789 ; gain = 166.391 ; free physical = 8660 ; free virtual = 44133 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing placer database... Phase 2.1 Fix Topology Constraints INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 2.1 Fix Topology Constraints | Checksum: 1a0edab69 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8597 ; free virtual = 44072 Phase 2.2 Pre Route Cleanup WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Phase 2.2 Pre Route Cleanup | Checksum: 1a0edab69 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8587 ; free virtual = 44064 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8555 ; free virtual = 44034 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 121342371 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8525 ; free virtual = 44013 Phase 3 Initial Routing Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8482 ; free virtual = 43966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 8481 ; free virtual = 43966 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8467 ; free virtual = 43952 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8455 ; free virtual = 43940 Phase 4 Rip-up And Reroute | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8450 ; free virtual = 43935 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8446 ; free virtual = 43932 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8439 ; free virtual = 43925 Phase 6 Post Hold Fix | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8435 ; free virtual = 43921 Phase 7 Route finalize Loading route data... Processing options... Creating bitmap... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8402 ; free virtual = 43889 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 121342371 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8396 ; free virtual = 43884 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 121342371 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 98.586 ; free physical = 8298 ; free virtual = 43789 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 98.586 ; free physical = 8334 ; free virtual = 43825 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2221.781 ; gain = 169.391 ; free physical = 8327 ; free virtual = 43818 Writing placer database... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1254.965 ; gain = 159.352 ; free physical = 8213 ; free virtual = 43714 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.789 ; gain = 0.000 ; free physical = 8138 ; free virtual = 43647 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 8052 ; free virtual = 43563 --------------------------------------------------------------------------------- Creating bitstream... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2129.430 ; gain = 21.223 ; free physical = 7981 ; free virtual = 43500 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2218.789 ; gain = 0.000 ; free physical = 7995 ; free virtual = 43486 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.418 ; gain = 27.211 ; free physical = 7968 ; free virtual = 43459 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.418 ; gain = 27.211 ; free physical = 7968 ; free virtual = 43459 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7846 ; free virtual = 43343 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7880 ; free virtual = 43378 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7878 ; free virtual = 43376 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7878 ; free virtual = 43376 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7878 ; free virtual = 43376 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7878 ; free virtual = 43376 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7878 ; free virtual = 43376 Phase 7 Route finalize Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7849 ; free virtual = 43349 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7849 ; free virtual = 43348 Phase 9 Depositing Routes INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2] Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7849 ; free virtual = 43349 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2154.473 ; gain = 46.266 ; free physical = 7883 ; free virtual = 43383 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:51 . Memory (MB): peak = 2193.262 ; gain = 85.055 ; free physical = 7882 ; free virtual = 43382 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Writing placer database... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1320] Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2221.781 ; gain = 0.000 ; free physical = 7829 ; free virtual = 43335 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2221.781 ; gain = 0.000 ; free physical = 7738 ; free virtual = 43230 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 7859 ; free virtual = 43366 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 7883 ; free virtual = 43391 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:38:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2533.363 ; gain = 338.105 ; free physical = 7787 ; free virtual = 43273 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:38:58 2019... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 7799 ; free virtual = 43285 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 7929 ; free virtual = 43415 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command write_bitstream Starting Placer Task Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads DONE INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 8833 ; free virtual = 44318 Loading site data... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. touch build/specimen_015/OK --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8756 ; free virtual = 44242 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.59 . Memory (MB): peak = 1547.961 ; gain = 0.000 ; free physical = 8755 ; free virtual = 44240 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8728 ; free virtual = 44214 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8726 ; free virtual = 44212 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8723 ; free virtual = 44209 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8722 ; free virtual = 44208 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8722 ; free virtual = 44208 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8722 ; free virtual = 44208 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8722 ; free virtual = 44208 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8723 ; free virtual = 44209 Creating bitstream... Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 8725 ; free virtual = 44211 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.867 ; gain = 342.105 ; free physical = 8270 ; free virtual = 43765 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:06 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 1436 #of tags: 192 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9180 ; free virtual = 44672 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2129.426 ; gain = 30.227 ; free physical = 9096 ; free virtual = 44608 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2135.414 ; gain = 36.215 ; free physical = 9054 ; free virtual = 44566 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2135.414 ; gain = 36.215 ; free physical = 9054 ; free virtual = 44566 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9027 ; free virtual = 44519 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9026 ; free virtual = 44519 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8994 ; free virtual = 44486 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8984 ; free virtual = 44476 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8970 ; free virtual = 44462 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8969 ; free virtual = 44462 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8968 ; free virtual = 44461 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8968 ; free virtual = 44460 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8968 ; free virtual = 44460 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8956 ; free virtual = 44449 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8956 ; free virtual = 44448 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8952 ; free virtual = 44444 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 8986 ; free virtual = 44479 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2193.258 ; gain = 94.059 ; free physical = 8986 ; free virtual = 44478 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 9002 ; free virtual = 44496 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1545.949 ; gain = 0.000 ; free physical = 8831 ; free virtual = 44334 Loading site data... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1545.949 ; gain = 0.000 ; free physical = 8814 ; free virtual = 44318 Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 8617 ; free virtual = 44132 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 1336.066 ; gain = 240.152 ; free physical = 8509 ; free virtual = 44003 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Loading site data... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1344.098 ; gain = 248.184 ; free physical = 8064 ; free virtual = 43559 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 8048 ; free virtual = 43543 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1344.098 ; gain = 248.184 ; free physical = 7944 ; free virtual = 43439 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing bitstream ./design.bit... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 8153 ; free virtual = 43652 Phase 1.3 Build Placer Netlist Model INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8164 ; free virtual = 43663 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... Loading data files... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8144 ; free virtual = 43643 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8143 ; free virtual = 43642 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8134 ; free virtual = 43633 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8132 ; free virtual = 43631 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8146 ; free virtual = 43645 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8167 ; free virtual = 43666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8167 ; free virtual = 43666 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.074 ; gain = 256.160 ; free physical = 8166 ; free virtual = 43665 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.082 ; gain = 256.160 ; free physical = 8167 ; free virtual = 43667 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 8099 ; free virtual = 43602 Phase 1.4 Constrain Clocks/Macros 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.367 ; gain = 339.105 ; free physical = 8128 ; free virtual = 43631 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:25 2019... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 8332 ; free virtual = 43834 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 455.203 ; free physical = 9394 ; free virtual = 44897 Phase 2 Global Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_016/OK INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1 Build RT Design | Checksum: 16ac86fd8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2134.070 ; gain = 49.668 ; free physical = 9356 ; free virtual = 44859 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9345 ; free virtual = 44849 Creating bitstream... Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9314 ; free virtual = 44818 Phase 3.2 Commit Most Macros & LUTRAMs Phase 2.1 Fix Topology Constraints | Checksum: 16ac86fd8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 9311 ; free virtual = 44814 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 16ac86fd8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2144.059 ; gain = 59.656 ; free physical = 9310 ; free virtual = 44814 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9303 ; free virtual = 44806 Phase 3.3 Area Swap Optimization Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.969 ; gain = 30.758 ; free physical = 9289 ; free virtual = 44792 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.957 ; gain = 36.746 ; free physical = 9245 ; free virtual = 44748 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.957 ; gain = 36.746 ; free physical = 9245 ; free virtual = 44748 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9234 ; free virtual = 44737 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 9219 ; free virtual = 44722 Phase 3.5 Small Shape Detail Placement Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e753ec2 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9214 ; free virtual = 44718 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9208 ; free virtual = 44711 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e753ec2 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9208 ; free virtual = 44712 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e753ec2 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9196 ; free virtual = 44700 Phase 4 Rip-up And Reroute | Checksum: 18e753ec2 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9195 ; free virtual = 44698 Phase 5 Delay and Skew Optimization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9194 ; free virtual = 44697 Phase 5 Delay and Skew Optimization | Checksum: 18e753ec2 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9193 ; free virtual = 44696 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9191 ; free virtual = 44695 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9191 ; free virtual = 44694 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9189 ; free virtual = 44693 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9188 ; free virtual = 44692 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9187 ; free virtual = 44691 Phase 7 Route finalize Phase 6.1 Hold Fix Iter | Checksum: 18e753ec2 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9191 ; free virtual = 44694 Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 6 Post Hold Fix | Checksum: 18e753ec2 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9189 ; free virtual = 44693 Phase 7 Route finalize INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9186 ; free virtual = 44690 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9184 ; free virtual = 44688 Phase 9 Depositing Routes Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9180 ; free virtual = 44684 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.012 ; gain = 54.801 ; free physical = 9215 ; free virtual = 44719 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2193.801 ; gain = 93.590 ; free physical = 9214 ; free virtual = 44718 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e753ec2 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9213 ; free virtual = 44716 Phase 8 Verifying routed nets WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e753ec2 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9203 ; free virtual = 44707 Phase 9 Depositing Routes Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:38 . Memory (MB): peak = 2607.949 ; gain = 389.160 ; free physical = 9184 ; free virtual = 44690 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:29 2019... INFO: [Project 1-570] Preparing netlist for logic optimization Phase 9 Depositing Routes | Checksum: 18e753ec2 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9197 ; free virtual = 44703 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.988 ; gain = 94.586 ; free physical = 9242 ; free virtual = 44749 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2217.777 ; gain = 165.391 ; free physical = 9242 ; free virtual = 44749 Writing bitstream ./design.bit... Writing placer database... Bitstream size: 4243411 bytes Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10320 ; free virtual = 45835 Phase 3.6 Re-assign LUT pins Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10356 ; free virtual = 45875 Phase 3.7 Pipeline Register Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10575 ; free virtual = 46097 touch build/specimen_017/OK Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10562 ; free virtual = 46088 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10386 ; free virtual = 45915 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10343 ; free virtual = 45874 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10313 ; free virtual = 45847 Phase 4.4 Final Placement Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10292 ; free virtual = 45827 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10269 ; free virtual = 45806 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 10288 ; free virtual = 45826 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.211 ; gain = 551.250 ; free physical = 10263 ; free virtual = 45802 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.211 ; gain = 631.953 ; free physical = 10263 ; free virtual = 45802 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.801 ; gain = 0.000 ; free physical = 10129 ; free virtual = 45678 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 10134 ; free virtual = 45685 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2217.777 ; gain = 0.000 ; free physical = 10134 ; free virtual = 45671 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:39 . Memory (MB): peak = 2607.902 ; gain = 386.121 ; free physical = 10154 ; free virtual = 45666 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:33 2019... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_018/OK Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 11110 ; free virtual = 46622 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 11107 ; free virtual = 46619 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.152 ; gain = 458.203 ; free physical = 11143 ; free virtual = 46655 Phase 2 Global Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11307 ; free virtual = 46823 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11341 ; free virtual = 46857 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11272 ; free virtual = 46788 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11287 ; free virtual = 46803 Phase 3.4 Pipeline Register Optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11279 ; free virtual = 46795 Phase 3.5 Small Shape Detail Placement Loading data files... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11104 ; free virtual = 46620 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11093 ; free virtual = 46610 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11080 ; free virtual = 46596 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11097 ; free virtual = 46613 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11078 ; free virtual = 46595 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11064 ; free virtual = 46581 Phase 4.3 Placer Reporting WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11056 ; free virtual = 46573 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11011 ; free virtual = 46527 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2533.363 ; gain = 340.105 ; free physical = 11002 ; free virtual = 46519 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:39 2019... Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11070 ; free virtual = 46587 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.195 ; gain = 546.246 ; free physical = 11769 ; free virtual = 47286 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 2092.195 ; gain = 623.949 ; free physical = 11842 ; free virtual = 47359 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:54 ; elapsed = 00:01:04 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 11956 ; free virtual = 47473 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1558.855 ; gain = 0.000 ; free physical = 11788 ; free virtual = 47305 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1558.855 ; gain = 0.000 ; free physical = 11785 ; free virtual = 47302 Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:18 . Memory (MB): peak = 2532.906 ; gain = 339.105 ; free physical = 11494 ; free virtual = 47016 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:50 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_018/OK Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 12464 ; free virtual = 47991 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 12419 ; free virtual = 47946 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:39:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:55 ; elapsed = 00:00:25 . Memory (MB): peak = 2607.938 ; gain = 390.160 ; free physical = 12403 ; free virtual = 47929 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:39:58 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2128.438 ; gain = 29.227 ; free physical = 13515 ; free virtual = 49041 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2135.426 ; gain = 36.215 ; free physical = 13478 ; free virtual = 49004 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2135.426 ; gain = 36.215 ; free physical = 13478 ; free virtual = 49004 touch build/specimen_019/OK Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13465 ; free virtual = 48991 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13469 ; free virtual = 48996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13469 ; free virtual = 48995 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13469 ; free virtual = 48995 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13469 ; free virtual = 48995 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13469 ; free virtual = 48995 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13469 ; free virtual = 48995 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13468 ; free virtual = 48995 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13467 ; free virtual = 48993 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13467 ; free virtual = 48993 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2154.480 ; gain = 55.270 ; free physical = 13502 ; free virtual = 49028 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2193.270 ; gain = 94.059 ; free physical = 13502 ; free virtual = 49028 Writing placer database... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 13490 ; free virtual = 49020 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 13485 ; free virtual = 49017 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 13482 ; free virtual = 49015 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 13477 ; free virtual = 49013 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2052.387 ; gain = 493.531 ; free physical = 13494 ; free virtual = 49032 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 13493 ; free virtual = 49030 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2193.270 ; gain = 0.000 ; free physical = 13450 ; free virtual = 49000 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 2131.426 ; gain = 39.230 ; free physical = 13170 ; free virtual = 48699 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 2137.414 ; gain = 45.219 ; free physical = 13120 ; free virtual = 48649 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 2137.414 ; gain = 45.219 ; free physical = 13120 ; free virtual = 48649 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13030 ; free virtual = 48558 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13017 ; free virtual = 48546 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13016 ; free virtual = 48544 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13016 ; free virtual = 48544 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13016 ; free virtual = 48544 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13015 ; free virtual = 48544 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13015 ; free virtual = 48544 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13007 ; free virtual = 48536 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13006 ; free virtual = 48534 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13003 ; free virtual = 48532 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:31 ; elapsed = 00:00:25 . Memory (MB): peak = 2157.469 ; gain = 65.273 ; free physical = 13037 ; free virtual = 48566 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:26 . Memory (MB): peak = 2196.258 ; gain = 104.062 ; free physical = 13036 ; free virtual = 48565 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2196.258 ; gain = 0.000 ; free physical = 12913 ; free virtual = 48464 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:40:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:22 ; elapsed = 00:00:15 . Memory (MB): peak = 2532.375 ; gain = 339.105 ; free physical = 12599 ; free virtual = 48134 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:40:16 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_019/OK Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 19e9914bc Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2135.070 ; gain = 50.668 ; free physical = 13916 ; free virtual = 49456 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19e9914bc Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 13879 ; free virtual = 49419 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19e9914bc Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2145.059 ; gain = 60.656 ; free physical = 13879 ; free virtual = 49418 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:40:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 2533.363 ; gain = 337.105 ; free physical = 13887 ; free virtual = 49427 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:40:22 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK Number of Nodes with overlaps = 0 /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Phase 2 Router Initialization | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14913 ; free virtual = 50453 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14913 ; free virtual = 50452 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14913 ; free virtual = 50453 Phase 4 Rip-up And Reroute | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14912 ; free virtual = 50452 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14912 ; free virtual = 50451 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14911 ; free virtual = 50451 Phase 6 Post Hold Fix | Checksum: 197d64bf1 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14911 ; free virtual = 50451 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 197d64bf1 Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14909 ; free virtual = 50449 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 197d64bf1 Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14907 ; free virtual = 50447 Phase 9 Depositing Routes Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 6936 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' Phase 9 Depositing Routes | Checksum: 197d64bf1 Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14905 ; free virtual = 50445 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 2181.363 ; gain = 96.961 ; free physical = 14949 ; free virtual = 50489 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:23 . Memory (MB): peak = 2220.152 ; gain = 167.766 ; free physical = 14948 ; free virtual = 50488 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2220.152 ; gain = 0.000 ; free physical = 14914 ; free virtual = 50482 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:40:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:21 . Memory (MB): peak = 2609.312 ; gain = 389.160 ; free physical = 14802 ; free virtual = 50352 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:40:45 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 39912 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' Makefile:116: recipe for target 'run' failed make[1]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid'